XPC8240RZU250E Freescale Semiconductor, XPC8240RZU250E Datasheet - Page 16

• Manufacturer Part Number: XPC8240RZU250E
• Description: MCU HOST PROCESSOR 352-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIr

Specifications of XPC8240RZU250E

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 352-TBGA
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 250MHz
• Embedded Interface Type: I2C
• Digital Ic Case Style: TBGA
• No. Of Pins: 352
• Supply Voltage Range: 2.5V To 2.75V
• Rohs Compliant: No
• Family Name: MPC82XX
• Device Core Size: 32b
• Frequency (max): 250MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.625/2.6255V
• Operating Supply Voltage (max): 2.75625/2.756775V
• Operating Supply Voltage (min): 2.49375/2.494225V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 352
• Package Type: TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

Electrical and Thermal Characteristics
Electrical and Thermal Characteristics
Figure 10 shows the input timing diagram for mode select signals.
1.4.2.4
Table 9 provides the processor bus AC timing specifications for the MPC8240. See Figure 8 and Figure 9
for the input-output timing diagrams referenced to SDRAM_SYNC_IN and PCI_SYNC_IN, respectively.
Figure 11 shows the AC test load for the MPC8240.
16
At recommended operating conditions (see Table 2) with LV
Num
12b1 SDRAM_SYNC_IN to output valid (for memory control address and
12b2 SDRAM_SYNC_IN to output valid (for memory control address and
12b3 SDRAM_SYNC_IN to output valid (for memory control address and
12a
12d
13a
13b
14a
12c
HRST_CPU/HRST_CTRL
PCI_SYNC_IN to output valid, 66 MHz PCI, with MCP in the default
logic 1 state and CKE pulled down to logic 0 state (see Figure 10)
PCI_SYNC_IN to output valid, 33 MHz PCI, with MCP and CKE in the
default logic 1 state (see Figure 10)
data signals accessing DRAM in flow-through mode)
data signals accessing DRAM in registered mode)
data signals accessing non-DRAM)
SDRAM_SYNC_IN to output valid (for all others)
SDRAM_SYNC_IN to output valid (for I
Output hold, 66 MHz PCI, with MCP in the default logic 1 state and
CKE pulled down to logic 0 state (see Figure 10)
Output hold, 33 MHz PCI, with MCP and CKE in the default logic 1
state (see Figure 10)
Output hold (all others)
PCI_SYNC_IN to output high impedance (for PCI)
Mode Pins
Output AC Timing Specification
Figure 10. Input Timing Diagram for Mode Select Signals
MPC8240 Integrated Processor Hardware Specifications
Freescale Semiconductor, Inc.
Characteristic
For More Information On This Product,
Table 9. Output AC Timing Specifications
Go to: www.freescale.com
VM = Midpoint Voltage (1.4 V)
2
C)
3, 6
10e
2.0 V
0.8 V
DD
= 3.3 V ± 0.3 V
VM
11b
Min
1.0
2.0
—
—
—
—
—
—
—
—
0
Max
14.0
6.0
8.0
7.0
6.0
7.0
7.0
5.0
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
2, 4, 5
2, 4, 5
2, 4
2, 4
2, 4
1
1
1
1
1
1