XPC8240RZU250E Freescale Semiconductor, XPC8240RZU250E Datasheet - Page 17

• Manufacturer Part Number: XPC8240RZU250E
• Description: MCU HOST PROCESSOR 352-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIr

Specifications of XPC8240RZU250E

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 352-TBGA
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 250MHz
• Embedded Interface Type: I2C
• Digital Ic Case Style: TBGA
• No. Of Pins: 352
• Supply Voltage Range: 2.5V To 2.75V
• Rohs Compliant: No
• Family Name: MPC82XX
• Device Core Size: 32b
• Frequency (max): 250MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.625/2.6255V
• Operating Supply Voltage (max): 2.75625/2.756775V
• Operating Supply Voltage (min): 2.49375/2.494225V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 352
• Package Type: TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

1.4.2.4.1
In order to meet minimum output hold specifications relative to PCI_SYNC_IN for both 33- and 66-MHz
PCI systems, the MPC8240 has a programmable output hold delay for PCI signals. The initial value of the
output hold delay is determined by the values on the MCP and CKE reset configuration signals. Further
output hold delay values are available through programming the PCI_HOLD_DEL value of the PMCR2
configuration register.
MPC8240 Integrated Processor Hardware Specifications
At recommended operating conditions (see Table 2) with LV
Notes:
1. All memory and related interface output signal specifications are specified from the VM = 1.4 V of the rising edge of
2. All PCI signals are measured from OV
3. All output timings assume a purely resistive 50-Ω load (see Figure 11). Output timings are measured at the pin;
4. PCI bused signals are composed of the following signals: LOCK, IRDY, C/BE[0:3], PAR, TRDY, FRAME, STOP,
5. PCI hold times can be varied; see Section 1.4.2.4.1, “PCI Signal Output Hold Timing,” for information on
6. These specifications are for the default driver strengths indicated in Table 4.
Num
14b
the memory bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0 V) of the signal in question.
SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode
(processor/memory bus clock rising edges occur on every rising and falling edge of PCI_SYNC_IN). See Figure 8.
of the signal in question for 3.3-V PCI signaling levels. See Figure 9.
time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
DEVSEL, PERR, SERR, AD[0:31], REQ[4:0], GNT[4:0], IDSEL, and INTA.
programmable PCI output hold times. The values shown for item 13a are for PCI compliance.
SDRAM_SYNC_IN to output high impedance (for all others)
PCI Signal Output Hold Timing
Output
Pin
Table 9. Output AC Timing Specifications (continued)
Freescale Semiconductor, Inc.
Characteristic
For More Information On This Product,
Figure 11. AC Test Load for the MPC8240
Z
0
= 50 Ω
Output Measurements are Made at the Device Pin
DD
Go to: www.freescale.com
/2 of the rising edge of PCI_SYNC_IN to 0.285 × OV
3, 6
DD
= 3.3 V ± 0.3 V
R
L
= 50 Ω
Electrical and Thermal Characteristics
OV
GV
Min
—
DD
DD
/2 for PCI
/2 for Memory
Max
4.0
DD
or 0.615 × OV
Unit
ns
Notes
1
DD
17