XPC8240RZU250E Freescale Semiconductor, XPC8240RZU250E Datasheet - Page 45

MCU HOST PROCESSOR 352-TBGA

XPC8240RZU250E

Manufacturer Part Number
XPC8240RZU250E
Description
MCU HOST PROCESSOR 352-TBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC IIr
Datasheets

Specifications of XPC8240RZU250E

Processor Type
MPC82xx PowerQUICC II 32-bit
Speed
200MHz
Voltage
2.5V
Mounting Type
Surface Mount
Package / Case
352-TBGA
Core Size
32 Bit
Program Memory Size
32KB
Cpu Speed
250MHz
Embedded Interface Type
I2C
Digital Ic Case Style
TBGA
No. Of Pins
352
Supply Voltage Range
2.5V To 2.75V
Rohs Compliant
No
Family Name
MPC82XX
Device Core Size
32b
Frequency (max)
250MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
2.625/2.6255V
Operating Supply Voltage (max)
2.75625/2.756775V
Operating Supply Voltage (min)
2.49375/2.494225V
Operating Temp Range
0C to 105C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
352
Package Type
TBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant

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17
and conduction) may vary widely. For these reasons, it is recommended that conjugate heat-transfer models
for the board, as well as system-level designs, be used.
1.8
Table 19 provides a revision history for this hardware specification.
MPC8240 Integrated Processor Hardware Specifications
Revision
Number
0.1
0.2
0
Document Revision History
Preliminary release with some TBDs in the spec tables.
Updated notes for Table 2.
Replaced TBDs in Table 3 with values for output high and low voltages.
Deleted 25/25/75 column from Table 5; inconsistent with PLL encoding 01000.
Updated minimum processor frequencies in Table 6 from 80 to 100 MHz.
Updated values in Table 8. Spec 10b split for flow through and registered modes.
Updated values in Table 9.
Updated PCI_HOLD_DEL value guidelines in Table 10 and Figure 10.
Relabeled DA[0:15] pins in opposite order and added Note 11 for TEST2 in Table 17.
Changed PLL configurations 01001 and 10001 in Table 18 to reserved configurations.
Updated PLL configuration 00010’s operation ranges in Table 18.
Revised TRST connection recommendations in Figure 22 for COP interface.
Added Note 4 to Table 2, updated Note and Caution numbers in Table 2 and Figure 2.
Modified Table 6:
—Added 250 MHz column.
—Changed Maximum PCI Input Frequency for 200 MHz part from 33 to 66 MHz.
—Made one column common entries for Memory Bus and PCI Input Frequencies.
Revised Note 7 of Table 7 to indicate a feedback loop length of 6.25 inches (formerly 11.8 inches)
corresponding to approximately 1 ns of delay.
Added 250 MHz column to Table 18.
Corrected document revision number for previous version of this document in Table 19. Document
revision was indicated as 1, should have been 0.1.
Removed P = Reduced Spec information from Figure 28; does not apply to MPC8240.
Added R = Modified Voltage Spec information to Figure 28.
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 19. Document Revision History
Go to: www.freescale.com
Substantive Change(s)
Document Revision History
45

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