XPC8240RZU250E Freescale Semiconductor, XPC8240RZU250E Datasheet - Page 4

• Manufacturer Part Number: XPC8240RZU250E
• Description: MCU HOST PROCESSOR 352-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIr

Specifications of XPC8240RZU250E

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 352-TBGA
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 250MHz
• Embedded Interface Type: I2C
• Digital Ic Case Style: TBGA
• No. Of Pins: 352
• Supply Voltage Range: 2.5V To 2.75V
• Rohs Compliant: No
• Family Name: MPC82XX
• Device Core Size: 32b
• Frequency (max): 250MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.625/2.6255V
• Operating Supply Voltage (max): 2.75625/2.756775V
• Operating Supply Voltage (min): 2.49375/2.494225V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 352
• Package Type: TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

Features
Features
4
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— Two-channel integrated DMA controller (writes to ROM/Port X not supported)
— Message unit
— I
— Programmable interrupt controller (PIC)
— Integrated PCI bus, CPU, and SDRAM clock generation
— Programmable PCI bus, 60x, and memory interface output drivers
Dynamic power management—Supports 60x nap, doze, and sleep modes
Programmable input and output signals with watchpoint capability
Built-in PCI bus performance monitor facility
— Debug features
Processor core interface
— High-performance, superscalar processor core
— Integer unit (IU), floating-point unit (FPU) (software enabled or disabled), load/store unit
— 16-Kbyte instruction cache
— 16-Kbyte data cache
— Lockable L1 cache, entire cache or on a per-way basis
– Address translation unit
– Some internal configuration registers accessible from PCI
– Supports direct mode or chaining mode (automatic linking of DMA transfers)
– Supports scatter gathering—Read or write discontinuous memory
– Interrupt on completed segment, chain, and error
– Local-to-local memory
– PCI-to-PCI memory
– PCI-to-local memory
– PCI memory-to-local memory
– Two doorbell registers
– Two inbound and two outbound messaging registers
– I
– Five hardware interrupts (IRQs) or 16 serial interrupts
– Four programmable timers
– Memory attribute and PCI attribute signals
– Debug address signals
– MIV signal—Marks valid address and data bus cycles on the memory bus
– Error injection/capture on data path
– IEEE 1149.1 (JTAG)/test interface
(LSU), system register unit (SRU), and a branch processing unit (BPU)
2
C controller with full master/slave support (except broadcast all)
2
O message controller
MPC8240 Integrated Processor Hardware Specifications
Freescale Semiconductor, Inc.
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