MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1152
![MPU POWERQUICC III 783-PBGA](/photos/37/62/376266/mpc8544e_image_sml.jpg)
MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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PCI Express Interface Controller
18.4.1
This section describes some of the implementation details of the PCI Express controller.
18.4.1.1
Table 18-117
target.
18-98
PCI Express
Transaction
CfgRd0
CfgWr0
CfgRd1
CfgWr1
MRdLk
MsgD
IORd
IOWr
CplD
MWr
Msg
Mrd
Cpl
Architecture
Supported as
Yes (RC only)
Yes (RC only)
Yes (RC only)
Yes (RC only)
Yes (RC only)
Yes (RC only)
Framing
PCI Express Transactions
Yes (RC only
contains the list of transactions that the PCI Express controller supports as an initiator and a
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
an Initiator
Yes
Yes
Yes
Yes
Yes
No
Sequence
Number
Supported as
Yes (EP only) Message Request with Data payload. Note that Set_Slot_Power_Limit is the
a Target
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
Figure 18-124. PCI Express Packet Flow
Table 18-117. PCI Express Transactions
Header
Memory Read Request
Memory Read Lock. As a target, CplLk with UR status is returned.
Memory Write Request to memory-mapped PCI-Express space
I/O Read request. As a target, Cpl with UR status is returned
I/O Write Request. As a target, Cpl with UR status is returned
Configuration Read Type 0
Configuration Write Type 0
Configuration Read Type 1. As a target, Cpl with UR status is returned.
Configuration Write Type 1. As a target, Cpl with UR status is returned.
Message Request
only message with data that is supported and then only when the controller is
an initiator and in RC mode or a target and in EP mode.
Completion without Data
Completion with Data
Transaction Layer
Data Link Layer
Physical Layer
Data
ECRC
Definition
LCRC
Freescale Semiconductor
Framing
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