MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 754

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
3
Enhanced Three-Speed Ethernet Controllers
15-22
0x2_4C20–
0x2_4C00–
0x2_5000–
0x2_4C0C RQPRM3*—Receive Queue Parameters register 3
0x2_4C1C RQPRM7*—Receive Queue Parameters register 7
0x2_4C4C RFBPTR1*—Last Free RxBD pointer for ring 1
0x2_4C5C RFBPTR3*—Last Free RxBD pointer for ring 3
0x2_4C6C RFBPTR5*—Last Free RxBD pointer for ring 5
0x2_4C7C RFBPTR7*—Last Free RxBD pointer for ring 7
0x2_4C00 RQPRM0*—Receive Queue Parameters register 0
0x2_4C04 RQPRM1*—Receive Queue Parameters register 1
0x2_4C08 RQPRM2*—Receive Queue Parameters register 2
0x2_4C10 RQPRM4*—Receive Queue Parameters register 4
0x2_4C14 RQPRM5*—Receive Queue Parameters register 5
0x2_4C18 RQPRM6*—Receive Queue Parameters register 6
0x2_4C40
0x2_4C44 RFBPTR0*—Last Free RxBD pointer for ring 0
0x2_4C48 Reserved
0x2_4C50 Reserved
0x2_4C54 RFBPTR2*—Last Free RxBD pointer for ring 2
0x2_4C58 Reserved
0x2_4C60 Reserved
0x2_4C64 RFBPTR4*—Last Free RxBD pointer for ring 4
0x2_4C68 Reserved
0x2_4C70 Reserved
0x2_4C74 RFBPTR6*—Last Free RxBD pointer for ring 6
0x2_4C78 Reserved
0x2_4D94
0x2_5FFF
eTSEC1
Registers denoted * are new to the enhanced TSEC and not supported by PowerQUICC III TSECs.
Key: R = read only, WO = write only, R/W = read and write, LH = latches high, SC = self-clearing.
Cleared on read.
Offset
Reserved
Reserved
eTSEC3 REGISTERS
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
4
Table 15-4. Module Memory Map (continued)
Name
eTSEC Lossless Flow Control Registers
eTSEC Future Expansion Space
1
eTSEC3
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
—
—
—
—
—
2
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
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Freescale Semiconductor
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