MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 50

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure
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10-9
10-10
10-11
10-12
10-13
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10-15
10-16
10-17
10-18
10-19
10-20
10-21
10-22
10-23
10-24
10-25
10-26
10-27
10-28
10-29
10-30
10-31
10-32
10-33
10-34
10-35
10-36
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10-38
10-39
10-40
10-41
10-42
10-43
10-44
10-45
10-46
10-47
10-48
11-1
l
IPI Vector/Priority Register (IPIVPRn) .............................................................................. 10-22
Spurious Vector Register (SVR) ......................................................................................... 10-23
Timer Frequency Reporting Register (TFRR) .................................................................... 10-23
Global Timer Current Count Registers (GTCCRn)............................................................. 10-24
Global Timer Base Count Register (GTBCRn)................................................................... 10-24
Global Timer Vector/Priority Register (GTVPRn).............................................................. 10-25
Global Timer Destination Registers (GTDRn).................................................................... 10-26
Example Calculation for Cascaded Timers......................................................................... 10-27
Timer Control Register (TCR) ............................................................................................ 10-27
External Interrupt Summary Register (ERQSR)................................................................. 10-29
IRQ_OUT Summary Register 0 (IRQSR0) ........................................................................ 10-29
IRQ_OUT Summary Register 1 (IRQSR1) ........................................................................ 10-30
IRQ_OUT Summary Register 2 (IRQSR2) ........................................................................ 10-30
Critical Interrupt Summary Register 0 (CISR0) ................................................................. 10-31
Critical Interrupt Summary Register 1 (CISR1) ................................................................. 10-31
Critical Interrupt Summary Register 2 (CISR2) ................................................................. 10-32
Performance Monitor n Mask Registers 0 (PMnMR0)....................................................... 10-32
Performance Monitor n Mask Registers 1 (PMnMR1)....................................................... 10-33
Performance Monitor n Mask Registers 2 (PMnMR2)....................................................... 10-34
Message Registers (MSGRs) .............................................................................................. 10-34
Message Enable Register (MER) ........................................................................................ 10-35
Message Status Register (MSR).......................................................................................... 10-35
Shared Message Signaled Interrupt Register (MSIRs) ....................................................... 10-36
Shared Message Signaled Interrupt Status Register (MSISR)............................................ 10-37
Shared Message Signaled Interrupt Index Register (MSIIR) ............................................. 10-37
Shared Message Signaled Interrupt Vector/Priority Register (MSIVPRn)......................... 10-38
Shared Message Signaled Interrupt Destination Registers (MSIDRn) ............................... 10-38
External Interrupt Vector/Priority Registers (EIVPR0–EIVPR11) ..................................... 10-39
External Interrupt Destination Registers (EIDRs) .............................................................. 10-40
Internal Interrupt Vector/Priority Registers (IIVPRs) ......................................................... 10-41
Internal Interrupt Destination Registers (IIDRs) ................................................................ 10-42
Messaging Interrupt Vector/Priority Registers (MIVPRs).................................................. 10-43
Messaging Interrupt Destination Registers (MIDRs) ......................................................... 10-44
Per-CPU Register Address Decoding in a Four-Core Device............................................. 10-45
Interprocessor Interrupt Dispatch Registers (IPIDR0–IPIDR3) ......................................... 10-46
Processor Current Task Priority Register (CTPR) .............................................................. 10-46
Processor Who Am I Register (WHOAMI)........................................................................ 10-47
Processor Interrupt Acknowledge Register (IACK) ........................................................... 10-47
End of Interrupt Register (EOI) .......................................................................................... 10-48
PIC Interrupt Processing Flow Diagram ............................................................................. 10-49
I
2
C Block Diagram................................................................................................................ 11-1
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
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