MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 241
![MPU POWERQUICC III 783-PBGA](/photos/37/62/376266/mpc8544e_image_sml.jpg)
MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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6.9
6.9.1
6.9.2
Freescale Semiconductor
Reset
Reset
32–61
62–63
32–61
SPR 513
SPR 514
Bits
Bits
62
63
W
R
W
R
32
32
target address
entry address
Branch buffer
Branch buffer
Branch Target Buffer (BTB) Registers
IAB[0–1]
BDIRPR
Name
Name
IAB2
Branch Buffer Entry Address Register (BBEAR)
Branch Buffer Target Address Register (BBTAR)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 6-30. Branch Buffer Target Address Register (BBTAR)
Figure 6-29. Branch Buffer Entry Address Register (BBEAR)
Branch buffer entry effective address bits 0–29
Instruction after branch (with BBTAR[62]). 3-bit pointer that points to the instruction in the cache line
after the branch. See the description in the bblels instruction in the EREF. If the branch is the last
instruction in the cache block, IAB = 000, to indicate the next sequential instruction, which resides in
the zeroth position of the next cache block.
Branch buffer target effective address bits 0–29
Instruction after branch bit 2 (with BBEAR[62–63]). IAB is a 3-bit pointer that points to the instruction
in the cache line after the branch. See the description for bblels in the EREF. If the branch is the last
instruction in the cache block, IAB = 000, to indicate the next sequential instruction, which resides in
the zeroth position of the next cache block.
Branch direction prediction. The user can pick the direction of the predicted branch.
0 The locked address is always predicted as not taken.
1 The locked address is always predicted as taken.
Table 6-15. BBEAR Field Descriptions
Table 6-16. BBTAR Field Descriptions
Branch buffer target address
Branch buffer entry address
All zeros
All zeros
Description
Description
Access: User read/write
Access: User read/write
Core Register Summary
61
IAB2 BDIRPR
62
61
IAB[0–1]
62
63
6-23
63
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