MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 247
![MPU POWERQUICC III 783-PBGA](/photos/37/62/376266/mpc8544e_image_sml.jpg)
MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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6.11.2
Freescale Semiconductor
Reset
56–61
32–46
49–51
SPR 1011
Bits
Bits
55
62
63
47
48
52
W
R
32
ICSLC Instruction cache snoop lock clear. Sticky bit set by hardware if an icbi snoop (either internally or externally
Name
Name
CLFR (Data) Cache lock bits flash reset. Writing a 1 during a flash clear operation causes an undefined operation.
ICPE
ICPI
CFI
CE
—
—
—
L1 Cache Control and Status Register 1 (L1CSR1)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Writing a 0 during a flash clear operation is ignored. Clearing occurs regardless of the enable (CE) value.
0 Default.
1 Hardware initiates a cache lock bits flash clear operation. This bit is cleared when the operation is
Reserved, should be cleared.
(Data) Cache flash invalidate.
0 No cache invalidate. Writing a 0 to CFI during an invalidation operation is ignored.
1 Cache invalidation operation. A cache invalidation operation is initiated by hardware. Once complete, this
Invalidation occurs regardless of the enable (CE) value.
(Data) Cache enable
0 The cache is neither accessed or updated.
1 Enables cache operation
Reserved, should be cleared.
Instruction cache parity enable
0 Parity checking of the instruction cache disabled
1 Parity checking of the instruction cache enabled
Instruction parity error injection enable
0 Parity error injection disabled
1 Parity error injection enabled. Note that instruction cache parity must also be enabled (ICPE = 1) when this
Reserved, should be cleared.
generated) invalidated a locked line in the instruction cache. Note that the lock bit for that line is cleared
whenever the line is invalidated. This bit can only be cleared by software.
0 The instruction cache has not encountered an icbi snoop that invalidated a locked line.
1 The instruction cache has encountered an icbi snoop that invalidated a locked line.
complete.
bit is cleared. Writing a 1 during an invalidation operation causes an undefined operation.
bit is set.
Figure 6-35. L1 Cache Control and Status Register 1 (L1CSR1)
—
Table 6-20. L1CSR0 Field Descriptions (continued)
Table 6-21. L1CSR1 Field Descriptions
46
ICPE ICPI
47
48
All zeros
49
—
Description
Description
51
ICSLC ICUL ICLO ICLFR
52
Line Locking Bits
53
54
55
Access: Supervisor read/write
56
Core Register Summary
—
61
ICFI ICE
62
6-29
63
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