MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 13
![MPU POWERQUICC III 783-PBGA](/photos/37/62/376266/mpc8544e_image_sml.jpg)
MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Paragraph
Number
8.1
8.1.1
8.1.2
8.2
8.2.1
8.2.1.1
8.2.1.2
8.2.1.3
8.2.1.4
8.2.1.5
8.2.1.6
8.2.1.7
8.2.1.8
8.2.1.9
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.4
9.1
9.2
9.2.1
9.3
9.3.1
9.3.2
9.3.2.1
9.3.2.2
9.3.2.3
9.4
Freescale Semiconductor
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Introduction...................................................................................................................... 8-1
Memory Map/Register Definition ................................................................................... 8-3
Functional Description..................................................................................................... 8-9
Initialization/Application Information ........................................................................... 8-10
Introduction...................................................................................................................... 9-1
Features ............................................................................................................................ 9-2
External Signal Descriptions ........................................................................................... 9-3
Memory Map/Register Definition ................................................................................... 9-9
Overview...................................................................................................................... 8-2
Features........................................................................................................................ 8-2
Register Descriptions................................................................................................... 8-3
I/O Arbiter.................................................................................................................... 8-9
CCB Arbiter................................................................................................................. 8-9
Transaction Queue ..................................................................................................... 8-10
Global Data Multiplexor............................................................................................ 8-10
CCB Interface ............................................................................................................ 8-10
Modes of Operation ..................................................................................................... 9-3
Signals Overview......................................................................................................... 9-3
Detailed Signal Descriptions ....................................................................................... 9-5
ECM CCB Address Configuration Register (EEBACR) ........................................ 8-3
ECM CCB Port Configuration Register (EEBPCR) ............................................... 8-4
ECM IP Block Revision Register 1 (EIPBRR1) ..................................................... 8-5
ECM IP Block Revision Register 2 (EIPBRR2) ..................................................... 8-5
ECM Error Detect Register (EEDR) ....................................................................... 8-6
ECM Error Enable Register (EEER) ....................................................................... 8-7
ECM Error Attributes Capture Register (EEATR) .................................................. 8-7
ECM Error Low Address Capture Register (EELADR) ......................................... 8-8
ECM Error High Address Capture Register (EEHADR) ........................................ 8-9
Memory Interface Signals........................................................................................ 9-5
Clock Interface Signals............................................................................................ 9-9
Debug Signals.......................................................................................................... 9-9
Memory, Security, and I/O Interfaces
e500 Coherency Module
DDR Memory Controller
Contents
Chapter 8
Chapter 9
Part III
Title
Number
Page
xiii
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