MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 185

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Part II
e500 Core Complex and L2 Cache
This part describes the many features of the MPC8544E core processor at an overview level and the
interaction between the core complex and the L2 cache. The following chapters are included:
The e500 processor core is a low-power implementation of the family of reduced instruction set computing
(RISC) embedded processors that implement the Power ISA definition. This part provides additional
information about the architecture as it relates specifically to the e500 core complex and specific details
on how its registers are accessed.
The e500 core complex interacts with the L2 cache through the core complex bus (CCB).
Freescale Semiconductor
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Chapter 5, “Core Complex Overview,”
L1 caches and MMU that, together with the core, comprise the core complex.
Chapter 6, “Core Register Summary,”
Chapter 7, “L2 Look-Aside Cache/SRAM,”
the L2 cache can also be addressed directly as memory-mapped SRAM.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
provides a listing of the e500v2 registers in reference form.
provides an overview of the e500v2 core processor and the
describes the L2 cache of the MPC8544E. Note that
II-1