MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 949
![MPU POWERQUICC III 783-PBGA](/photos/37/62/376266/mpc8544e_image_sml.jpg)
MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
0x148
•
•
•
Offset
0x10C
0x11C
0x13C
0x17C
0x18C
0x19C
0x100
0x104
0x108
0x110
0x114
0x118
0x120
0x124
0x128
0x130
0x134
0x138
0x140
0x144
0x180
0x184
0x188
0x190
0x194
0x198
w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
–
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
MR0—DMA 0 mode register
SR0—DMA 0 status register
ECLNDAR0—DMA 0 current link descriptor extended
address register
CLNDAR0—DMA 0 current link descriptor address register
SATR0—DMA 0 source attributes register
SAR0—DMA 0 source address register
DATR0—DMA 0 destination attributes register
DAR0—DMA 0 destination address register
BCR0—DMA 0 byte count register
ENLNDAR0—DMA 0 next link descriptor extended address
register
NLNDAR0—DMA 0 next link descriptor address register
ECLSDAR0—DMA 0 current list descriptor extended
address register
CLSDAR0—DMA 0 current list descriptor address register
ENLSDAR0—DMA 0 next list descriptor extended address
register
NLSDAR0—DMA 0 next list descriptor address register
SSR0—DMA 0 source stride register
DSR0—DMA 0 destination stride register
Reserved
MR1—DMA 1 mode register
SR1—DMA 1 status register
ECLNDAR1—DMA 1 current link descriptor extended
address register
CLNDAR1—DMA 1 current link descriptor address register
SATR1—DMA 1 source attributes register
SAR1—DMA 1 source address register
DATR1—DMA 1 destination attributes register
DAR1—DMA 1 destination address register
DMA Controller Block Base Address: 0x2_1000
Table 16-4. DMA Register Summary
Register
Access
Mixed
Mixed
Mixed
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
16.3.1.10/16-21
16.3.1.10/16-21
16.3.1.11/16-22
16.3.1.11/16-22
16.3.1.12/16-22
16.3.1.13/16-23
16.3.1.1/16-10
16.3.1.2/16-12
16.3.1.3/16-13
16.3.1.3/16-13
16.3.1.4/16-15
16.3.1.5/16-16
16.3.1.6/16-17
16.3.1.7/16-18
16.3.1.8/16-19
16.3.1.9/16-19
16.3.1.9/16-19
16.3.1.1/16-10
16.3.1.2/16-12
16.3.1.3/16-13
16.3.1.3/16-13
16.3.1.4/16-15
16.3.1.5/16-16
16.3.1.6/16-17
16.3.1.7/16-18
Section/Page
DMA Controller
—
16-7
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