MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 316
![MPU POWERQUICC III 783-PBGA](/photos/37/62/376266/mpc8544e_image_sml.jpg)
MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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e500 Coherency Module
Table 8-2
8.2.1.2
The ECM CCB port configuration register (EEBPCR) is shown in
Table 8-3
8-4
Offset 0x0_1010
Reset 0 0 0 0 0 0 0
8–28
Bits
0–6
30–31
0–27
7
Bits
W
R
28
29
0
CORE_STRM_DIS With A_STRM_DIS, controls whether the e500 core can stream commands onto the CCB.
describes the EEBACR fields.
describes EEBPCR fields.
A_STRM_CNT
CPU_EN
A_STRM_DIS
Name
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
—
—
ECM CCB Port Configuration Register (EEBPCR)
Name
—
6
CPU_EN
Figure 8-3. ECM CCB Port Configuration Register (EEBPCR)
Reserved
CPU port enable. Controls boot holdoff mode when the device is an agent of an external host.
Specifies whether the e500 core (CPU) port is enabled to run transactions on the CCB. The CPU
boot configuration power-on reset pin (cfg_cpu_boot) determines the initial value of this bit. If the
pin is sampled as a logic 1 at the negation of reset, the CPU is enabled to boot at the end of the
POR sequence. Otherwise, the CPU cannot fetch its boot vector until an external host sets the
CPU_EN bit.
0 Boot holdoff mode. CPU arbitration is disabled on the CCB and no bus grants are issued.
1 CPU is enabled and receives bus grants in response to bus requests for the boot vector.
After this bit is set, it should not be cleared by software. It is not intended to dynamically enable
and disable CPU operation. It is only intended to end boot holdoff mode. See
“CPU Boot
Reserved
n
7
Reserved
Controls whether the ECM allows any streaming to occur.
0 Streaming is enabled.
1 Streaming is disabled.
A_STRM_DIS and CORE_STRM_DIS must both be cleared for the e500 core to be enabled
to stream address tenures that it masters.
0 Stream address tenures initiated by the e500 core, provided A_STRM_DIS is cleared.
1 Streaming of address tenures initiated by the e500 core not allowed.
Stream count. Specifies the maximum number of transactions that any master can stream
(issue sequentially without preemption) on the CCB following an initial transaction.
00 Reserved
01 One transaction can be streamed with the initial transaction.
10 Two transactions can be streamed with the initial transaction.
11 Three transactions can be streamed with the initial transaction. Default.
8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Configuration,” for more information.
Table 8-2. EEBACR Field Descriptions
Table 8-3. EEBPCR Field Descriptions
—
Description
Description
Figure
8-3.
28
CPU_RD_HI_DIS CPU_PRI
Freescale Semiconductor
29
0
Access: Read/Write
Section 4.4.3.7,
30
0
31
0
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