MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 67
![MPU POWERQUICC III 783-PBGA](/photos/37/62/376266/mpc8544e_image_sml.jpg)
MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 67 of 1340
- Download datasheet (12Mb)
Table
Number
i
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
3-1
3-2
3-3
3-4
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
Freescale Semiconductor
Acronyms and Abbreviated Terms.........................................................................................xciv
Target Interface Codes ............................................................................................................ 2-1
Local Access Windows Example............................................................................................ 2-2
Format of ATMU Window Definitions................................................................................... 2-3
Local Access Register Memory Map...................................................................................... 2-5
LAIPBRR1 Field Descriptions ............................................................................................... 2-6
LAIPBRR2 Field Descriptions ............................................................................................... 2-6
LAWBARn Field Descriptions ............................................................................................... 2-7
LAWARn Field Descriptions .................................................................................................. 2-7
Overlapping Local Access Windows ...................................................................................... 2-8
Local Memory Configuration, Control, and Status Register Summary................................ 2-11
CCSR Block Base Address Map........................................................................................... 2-15
MPC8544E Signal Reference by Functional Block................................................................ 3-5
MPC8544E Alphabetical Signal Reference.......................................................................... 3-10
MPC8544E Reset Configuration Signals.............................................................................. 3-16
Output Signal States During System Reset ........................................................................... 3-17
Signal Summary ...................................................................................................................... 4-1
System Control Signals—Detailed Signal Descriptions ......................................................... 4-2
Clock Signals—Detailed Signal Descriptions ........................................................................ 4-3
Local Configuration Control Register Map ............................................................................ 4-4
CCSRBAR Bit Settings .......................................................................................................... 4-5
ALTCBAR Bit Settings........................................................................................................... 4-6
ALTCAR Bit Settings ............................................................................................................. 4-7
BPTR Bit Settings ................................................................................................................... 4-8
CCB Clock PLL Ratio .......................................................................................................... 4-12
e500 Core Clock PLL Ratios ................................................................................................ 4-12
SEC Mode Configuration...................................................................................................... 4-13
Boot ROM Location.............................................................................................................. 4-13
Host/Agent Configuration..................................................................................................... 4-14
I/O Port Selection.................................................................................................................. 4-15
CPU Boot Configuration....................................................................................................... 4-17
Boot Sequencer Configuration.............................................................................................. 4-17
DDR DRAM Type ................................................................................................................ 4-18
eTSEC1 Serial Configuration ............................................................................................... 4-18
eTSEC3 Serial Configuration ............................................................................................... 4-18
eTSEC1/eTSEC2 Width Configuration ................................................................................ 4-19
eTSEC3/eTSEC4 Width Configuration ................................................................................ 4-19
eTSEC1 Protocol Configuration ........................................................................................... 4-20
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Tables
Title
Tables
Number
Page
lxvii
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