MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1173

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.4.1.3
PORIMPSCR, shown in
interfaces.
The I/O impedance of local bus signals (including the local bus clock) is controlled through this register.
The I/O impedance of PCI signals is controlled by POR configuration pins (described in
“PCI I/O
impedances.
Table 19-6
Freescale Semiconductor
16–24
25–31 LBC_Z I/O impedance for these local bus signals: LAD[0:31], LDP[0:3], LA[27:31], LCS[1:2], LWE[0:3], LGPL[0:5],
13–15
16–31
0–14
Bits
Bits
Offset 0xE_0008
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15
W
R
0
PCI_Z PCI I/O impedance
Name
Impedance”). The MPC8544E Integrated Processor Hardware Specification provides exact I/O
Name
—
—
HA
—
describes PORIMPSCR fields.
POR I/O Impedance Status and Control Register (PORIMPSCR)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
0 Low impedance
1 High impedance
Reserved
LCKE, LCLK[0:2]
Note: Other signals (for example, LALE, LCS[0], LCS[3:7]) use a fixed high I/O impedance
1111111 High impedance
else Low impedance
Figure 19-3. POR I/O Impedance Status and Control Register (PORIMPSCR)
Host/agent mode configuration. When the MPC8544E is an agent on an interface, it is prevented from
mastering transactions on that interface until the external host configures the interface appropriately.
000 Reserved
001 PCI Express 3 endpoint
010 Reserved
011 PCI Express 2 endpoint
100 Reserved
101 PCI Express 1 endpoint
110 PCI Agent
111 Host mode/Root complex
Reserved
Figure
Table 19-5. PORBMSR Field Descriptions (continued)
—
Table 19-6. PORIMPSCR Field Descriptions
19-3,contains the current I/O driver impedances for local bus and PCI
14
n
PCI_Z
Description
15
n
Description
16
0 0
0
0
—
0
0
0
0 0 1 1 1 1 1 1 1
24 25
Section 4.4.3.18,
Access: Mixed
LBC_Z
Global Utilities
19-7
31