MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 108
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MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
System Design Information
21.5
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. All unused active low inputs should be tied to V
required. All unused active high inputs should be connected to GND. All NC (no connect) signals must
remain unconnected. Power and ground connections must be made to all external V
OV
21.6
The MPC8544E requires weak pull-up resistors (2–10 kΩ is recommended) on open drain type pins
including I
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in
state under normal operating conditions as most have asynchronous behavior and spurious assertion will
give unpredictable results.
The following pins must NOT be pulled down during power-on reset: TSEC3_TXD[3], HRESET_REQ,
TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. The DMA_DACK[0:1] and TEST_SEL pins
must be set to a proper state during POR configuration. Refer to the pinout listing table
details. Refer to the PCI 2.2 Local Bus Specifications, for all pullups required for PCI.
21.7
The MPC8544E drivers are characterized over process, voltage, and temperature. For all buses, the driver
is a push-pull single-ended driver type (open drain for I
an external resistor is connected from the chip pad to OV
varied until the pad voltage is OV
components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed
(SW2 is open) and R
108
DD
, GV
Connection Recommendations
Pull-Up and Pull-Down Resistor Requirements
Output Buffer DC Impedance
2
DD
C pins and MPIC interrupt pins.
, and LV
Figure
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
P
is trimmed until the voltage at the pad equals OV
DD
69. Care must be taken to ensure that these pins are maintained at a valid deasserted
, and GND pins of the device.
DD
/2 (see
Figure
67). The output impedance is the average of two
DD
2
C). To measure Z
, TV
DD
or GND. Then, the value of each resistor is
DD
, BV
DD
DD
, OV
0
/2. R
for the single-ended drivers,
DD
P
, GV
then becomes the
DD
Freescale Semiconductor
DD
(Table
, TV
, and LV
DD
62) for more
, BV
DD
DD
as
,