MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 39

MPU POWERQUICC III 783-PBGA

MPC8544VTALF

Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8544VTALF

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Figure 22
Freescale Semiconductor
At recommended operating conditions with L/TV
Fall time (20%–80%)
Notes:
1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII and
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
3. For 10 and 100 Mbps, t
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
5. Guaranteed by design.
RTBI timing. For example, the subscript of t
(R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is
skew (SK) followed by the clock that is being skewed (RGT).
will be added to the associated clock signal.
as the minimum duty cycle is not violated and stretching occurs for no more than three t
between.
(At Transmitter)
shows the RGMII and RTBI AC timing and multiplexing diagrams.
RXD[8:5][3:0]
RXD[7:4][3:0]
TXD[8:5][3:0]
TXD[7:4][3:0]
(At Receiver)
Parameter/Condition
GTX_CLK
GTX_CLK
(At PHY)
(At PHY)
RX_CTL
RX_CLK
TX_CLK
TX_CTL
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Figure 22. RGMII and RTBI AC Timing and Multiplexing Diagrams
Table 37. RGMII and RTBI AC Timing Specifications (continued)
RGT
scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
RXD[3:0]
TXD[3:0]
DD
RXD[4]
TXD[4]
TXEN
RXDV
of 2.5 V ± 5%.
RGT
represents the TBI (T) receive (RX) clock. Note also that the notation for rise
RXD[8:5]
RXD[7:4]
TXD[8:5]
TXD[7:4]
RXERR
TXERR
RXD[9]
TXD[9]
Symbol
t
RGTF
1
t
t
Enhanced Three-Speed Ethernet (eTSEC), MII Management
SKRGT_TX
SKRGT_TX
Min
t
t
RGTH
RGTH
Typ
RGT
t
t
of the lowest speed transitioned
RGT
RGT
Max
0.75
t
t
SKRGT_RX
SKRGT_RX
Unit
ns
Notes
39

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