MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 80
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MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
PCI Express
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the
TX UI.
17.5.1
The AC timing and voltage parameters must be verified at the measurement point, as specified within
0.2 inches of the package pins, into a test/measurement load shown in
80
Compliance Test and Measurement Load
Figure 57. Minimum Receiver Eye Timing and Voltage Compliance Specification
The reference impedance for return loss measurements is 50 Ω to ground for
both the D+ and D– line (that is, as measured by a vector network analyzer
with 50-Ω probes, see
optional for the return loss measurement.
The allowance of the measurement point to be within 0.2 inches of the
package pins is meant to acknowledge that package/board routing may
benefit from D+ and D– not being exactly matched in length at the package
pin boundary.
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
(D+ D– Crossing Point)
V
RX-DIFF
D+ Package
D+ Package
D– Package
= 0 mV
Figure 58. Compliance Test/Measurement Load
+ Package
Silicon
Pin
Pin
Pin
TX
Figure
V
RX-DIFFp-p-MIN
0.4 UI = T
57). Note that the series capacitors, CTX, are
C = C
C = C
NOTE
NOTE
R = 50 Ω
RX-EYE-MIN
TX
TX
> 175 mV
(D+ D– Crossing Point)
R = 50 Ω
V
Figure
RX-DIFF
58.
= 0 mV
Freescale Semiconductor