MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 11
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MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Figure 2
The core voltage must always be provided at nominal 1.0 V (see
voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must
be provided at the voltages shown in
associated I/O supply voltage. OV
appropriate LVCMOS type specifications. The DDR2 SDRAM interface uses a single-ended differential
receiver referenced the externally supplied MV
the SSTL2 electrical signaling standard.
Freescale Semiconductor
shows the undershoot and overshoot voltages at the interfaces of the MPC8544E.
V
Notes:
Figure 2. Overshoot/Undershoot Voltage for GV
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
IH
1. t
2. Please note that with the PCI overshoot allowed (as specified above), the device
does not fully comply with the maximum AC ratings and device protection
guideline outlined in Section 4.2.2.3 of the PCI 2.2 Local Bus Specifications.
CLOCK
For I
For DDR, t
For eTSEC, t
For LBIU, t
For PCI, t
V
B/G/L/OV
IL
B/G/L/OV
2
C and JTAG, t
refers to the clock period associated with the respective interface:
GND – 0.3 V
GND – 0.7 V
B/G/L/OV
CLOCK
CLOCK
CLOCK
DD
DD
CLOCK
+ 20%
+ 5%
GND
DD
references PCI_CLK or SYSCLK.
references MCLK.
references LCLK.
DD
CLOCK
references EC_GTX_CLK125.
Table
and LV
references SYSCLK.
2. The input voltage threshold scales with respect to the
DD
REF
based receivers are simple CMOS I/O circuits and satisfy
signal (nominally set to GV
Not to Exceed 10%
of t
CLOCK
DD
Table 2
/OV
1
DD
/LV
for actual recommended core
DD
/BV
DD
DD
/2) as is appropriate for
/TV
Electrical Characteristics
DD
11