MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 37
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MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Figure 20
8.7.3
When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant
eTSEC interface. In single-clock TBI mode, when TBICON[CLKSEL] = 1, a 125-MHz TBI receive clock
is supplied on the TSECn_RX_CLK pin (no receive clock is used on TSECn_TX_CLK in this mode,
whereas for the dual-clock mode this is the PMA1 receive clock). The 125-MHz transmit clock is applied
on the TSEC_GTX_CLK125 pin in all TBI modes.
Freescale Semiconductor
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%.
PMA_RX_CLK[0:1] duty cycle
RCG[9:0] setup time to rising PMA_RX_CLK
PMA_RX_CLK to RCG[9:0] hold time
PMA_RX_CLK[0:1] clock rise time (20%-80%)
PMA_RX_CLK[0:1] clock fall time (80%-20%)
Note:
1. The symbols used for timing specifications follow the pattern of t
inputs and t
timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
going to the high (H) state or setup time. Also, t
signals (D) went invalid (X) relative to the t
reference symbol representation is based on three letters representing the clock of a particular functional. For example, the
subscript of t
appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that
is being skewed (TRX).
shows the TBI receive AC timing diagram.
TBI Single-Clock Mode AC Specifications
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter/Condition
PMA_RX_CLK1
PMA_RX_CLK0
TRX
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the
RCG[9:0]
Table 35. TBI Receive AC Timing Specifications (continued)
Figure 20. TBI Receive AC Timing Diagram
t
t
SKTRX
TRXH
t
TRDVKH
TRX
clock reference (K) going to the high (H) state. Note that, in general, the clock
TRDXKH
t
TRX
t
Symbol
TRXH
t
t
t
TRXH
TRDVKH
TRDXKH
t
t
symbolizes TBI receive timing (TR) with respect to the time data input
TRXR
TRXF
/t
Valid Data
TRX
1
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
t
TRXF
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Min
2.5
1.5
0.7
0.7
40
Valid Data
t
TRDXKH
t
TRXR
t
Typ
TRDVKH
—
—
—
—
—
t
TRDXKH
TRDVKH
Max
2.4
2.4
60
—
—
TRX
symbolizes TBI receive
clock reference (K)
Unit
ns
ns
ns
ns
%
Notes
—
—
—
—
—
for
37