Z0840004PSC Zilog, Z0840004PSC Datasheet - Page 35

• Manufacturer Part Number: Z0840004PSC
• Description: IC 4MHZ Z80 NMOS CPU 40-DIP
• Manufacturer: Zilog

Specifications of Z0840004PSC

• Processor Type: Z80
• Features: NMOS
• Speed: 4MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ZiLOG
2002 Quality and Reliability Report
ESD TESTING METHODOLOGY
ZiLOG has an unqualified commitment to quality and reliability and, as part of this commitment,
ZiLOG strives to provide the best possible ESD protection for each of our products.
Since 1983, ZiLOG has had an ongoing electrostatic discharge development program to monitor
and improve its ESD protection circuitry. During an ESD event, the ESD protection circuitry must
absorb the power of the ESD pulse while allowing little or no damage to occur to the internal
circuitry of the chip. A 3000 volt ESD pulse can induce transient currents approaching one amp,
and it is the management of these transient currents that is the key to good ESD protection. At
ZiLOG, ESD protection circuits have been developed to optimize the handling of ESD pulse
currents, by paying close attention to current flow patterns, and minimizing current density and
crowding problems that cause damage to the circuitry. This circuitry has resulted in typical ESD
failure voltages above 2000 volts for NMOS products and above 4000 volts for CMOS products,
with concomitant improvement in product quality and reliability.
All of ZiLOG’s products are tested for their ESD immunity as part of routine internal qualification
procedures. The ESD test hardware is in compliance with MIL-STD-883 and Method 3015.7.
LATCHUP TESTING METHODOLOGY
ZiLOG has an unqualified commitment to quality and reliability and, as part of this commitment,
also strives to provide each of its products with the best possible latchup protection.
ZiLOG has an ongoing program to monitor and improve its latchup protection circuitry. Latchup
may occur as a result of either current injection (positive or negative) or supply pin overvoltage.
The latchup action is that of a parasitic SCR, converting from a high-impedance state, to a low
impedance, regenerative, state. The resulting current flow may exceed the design capabilities of
the device. Damage may occur to interconnections (bond wires and die metallization) as a result of
thermal heating effects and excessive current flow.
During conditions, which may lead to latchup, the device must be able to shunt the triggering event
(the positive or negative injection current) without damage to the device. ZiLOG has targeted a
200 mA minimum latchup requirement for all new designs to minimize the risk of latchup. In
addition, ZiLOG recommends that the customer do a careful analysis of system transients to ensure
that our maximum undershoot and overshoot applied potentials are not violated.
Absolute
maximum ratings are: voltage on Vcc with respect to V
– 0.3V to +7.0V and voltages on all
SS
inputs with respect to V
– 0.3 to V
+ 0.3V.
SS
CC
All of ZiLOG’s products are tested for their latchup immunity as part of routine internal
qualification procedures. The latchup test hardware is in compliance with EIA JEDEC Standard
78, and the detailed test procedure is per ZiLOG specification QCC1425, which is available upon
request.
ZAC03-0004
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