MC68EC020FG25 Freescale Semiconductor, MC68EC020FG25 Datasheet - Page 114

IC MPU 32 BIT 25MHZ 100-QFP

MC68EC020FG25

Manufacturer Part Number
MC68EC020FG25
Description
IC MPU 32 BIT 25MHZ 100-QFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68EC020FG25

Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-

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5.7.1.4 BUS ARBITRATION CONTROL (MC68020). The bus arbitration control unit in the
MC68020 is implemented with a finite state machine. As discussed previously, all
asynchronous inputs to the MC68020 are internally synchronized in a maximum of two
cycles of the processor clock.
As shown in Figure 5-44, input signals labeled R and A are internally synchronized
versions of the BR and BGACK signals, respectively. The BG output is labeled G, and the
internal high-impedance control signal is labeled T. If T is true, the address, data, and
control buses are placed in the high-impedance state after the next rising edge following
the negation of AS and RMC. All signals are shown in positive logic (active high),
regardless of their true active voltage level.
MOTOROLA
Figure 5-44. MC68020 Bus Arbitration State Diagram
NOTE: The BG output will not be asserted while RMC is asserted.
R—BUS REQUEST
A—BUS GRANT ACKNOWLEDGE
G—BUS GRANT
T—THREE-STATE CONTROL TO BUS CONTROL LOGIC
X—DON'T CARE
XX
RA
STATE 1
STATE 2
GT
GT
RA
RA
RA
M68020 USER’S MANUAL
XA
RA
STATE 0
STATE 3
STATE 6
GT
GT
GT
RX
RA
RA
XX
XA
XX
STATE 4
STATE 5
GT
GT
RX
RA
5- 67

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