MC68EC020FG25 Freescale Semiconductor, MC68EC020FG25 Datasheet - Page 231
MC68EC020FG25
Manufacturer Part Number
MC68EC020FG25
Description
IC MPU 32 BIT 25MHZ 100-QFP
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68EC020AA16.pdf
(306 pages)
Specifications of MC68EC020FG25
Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
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8.2.4 Calculate Immediate Effective Address
The calculate immediate effective address table indicates the number of clock periods
needed for the processor to fetch the immediate source operand and calculate the
specified destination effective address. Fetch time is only included for the first level of
indirection on memory indirect addressing modes. The total number of clock cycles is
outside the parentheses; the number of read, prefetch, and write cycles is given inside the
parentheses as (r/p/w). These cycles are included in the total clock cycle number.
MOTOROLA
#<data >.W,Dn
#<data >.L,Dn
#<data >.W,(An)
#<data >.L,(An)
#<data >.W,(An)+
#<data >.L,(An)+
#<data >.W,(bd,An)
#<data >.L,(bd,An)
#<data >.W,xxx.W
#<data >.L,xxx.W
#<data >.W,xxx.L
#<data >.L,xxx.L
#<data >.W,(d
#<data >.L,(d
#<data >.W,(d
#<data >.L,(d
#<data >.W,(B)
#<data >.L,(B)
#<data >.W,(bd,PC)
#<data >.L,(bd,PC)
#<data >.W,(d
#<data >.L,(d
#<data >.W,(d
#<data >.L,(d
#<data >.W,([B],I)
#<data >.L,([B],I)
#<data >.W,([B],I,d
#<data >.L,([B],I,d
#<data >.W,([B],I,d
#<data >.L,([d 16 ,B],I,d
#<data >.W,([d
#<data >.L,([d
#<data >.W,([d
16
16
32
8
16
16
16
32
8
,An,Xn) or (d
16
16
,An,Xn) or (d
,An,Xn) or (d
,B)
,B)
,B],I)
,An,Xn) or (d
,B)
,B)
,B],I)
,B],I,d
16
16
32
)
)
)
32
16
Address Mode
)
)
8
8
,PC,Xn)
16
,PC,Xn)
16
,PC,Xn)
,PC,Xn)
M68020 USER’S MANUAL
Best Case
10(0/0/0)
10(0/0/0)
10(1/0/0)
11(1/0/0)
10(1/0/0)
11(1/0/0)
10(1/0/0)
11(1/0/0)
12(1/0/0)
0(0/0/0)
1(0/0/0)
0(0/0/0)
1(0/0/0)
2(0/0/0)
3(0/0/0)
1(0/0/0)
3(0/0/0)
1(0/0/0)
3(0/0/0)
2(0/0/0)
3(0/0/0)
0(0/0/0)
2(0/0/0)
3(0/0/0)
4(0/0/0)
3(0/0/0)
4(0/0/0)
9(0/0/0)
5(0/0/0)
6(0/0/0)
9(0/0/0)
8(1/0/0)
9(1/0/0)
Cache Case
10(0/0/0)
10(0/0/0)
14(0/0/0)
16(0/0/0)
10(0/0/0)
12(0/0/0)
14(0/0/0)
16(0/0/0)
13(1/0/0)
15(1/0/0)
15(1/0/0)
17(1/0/0)
15(1/0/0)
17(1/0/0)
15(1/0/0)
17(1/0/0)
17(1/0/0)
2(0/0/0)
4(0/0/0)
2(0/0/0)
4(0/0/0)
4(0/0/0)
6(0/0/0)
4(0/0/0)
6(0/0/0)
4(0/0/0)
6(0/0/0)
4(0/0/0)
8(0/0/0)
6(0/0/0)
8(0/0/0)
8(0/0/0)
8(0/0/0)
Worst Case
10(0/2/0)
10(0/2/0)
10(0/2/0)
12(0/2/0)
10(0/1/0)
12(0/2/0)
18(0/3/0)
20(0/3/0)
13(0/2/0)
15(0/2/0)
18(0/2/0)
20(0/3/0)
15(1/2/0)
17(1/2/0)
18(1/2/0)
20(1/2/0)
19(1/2/0)
21(1/3/0)
18(1/2/0)
20(1/2/0)
21(1/2/0)
3(0/1/0)
5(0/1/0)
3(0/1/0)
5(0/1/0)
5(0/1/0)
7(0/1/0)
5(0/1/0)
8(0/2/0)
5(0/1/0)
8(0/2/0)
6(0/2/0)
8(0/2/0)
8- 17
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