MC68EC020FG25 Freescale Semiconductor, MC68EC020FG25 Datasheet - Page 44

• Manufacturer Part Number: MC68EC020FG25
• Description: IC MPU 32 BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020FG25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

SECTION 4
ON-CHIP CACHE MEMORY
The MC68020/EC020 incorporates an on-chip cache memory as a means of improving
performance. The cache is implemented as a CPU instruction cache and is used to store
the instruction stream prefetch accesses from the main memory.
An increase in instruction throughput results when instruction words required by a
program are available in the on-chip cache and the time required to access them on the
external bus is eliminated. In systems with more than one bus master (e.g., a processor
and a DMA device), reduced external bus activity increases overall performance by
increasing the availability of the bus for use by external devices without degrading the
performance of the MC68020/EC020.
4.1 ON-CHIP CACHE ORGANIZATION AND OPERATION
The MC68020/EC020 on-chip instruction cache is a direct-mapped cache of 64 long-word
entries. Each cache entry consists of a tag field (A31–A8 and FC2), one valid bit, and 32
bits (two words) of instruction data. Figure 4-1 shows a block diagram of the on-chip
cache organization.
Externally, the MC68EC020 does not use the upper eight bits of the address (A31–A24),
and addresses $FF000000 and $00000000 from the MC68EC020 appear the same.
However, the MC68EC020 does use A31–A24 internally in the instruction cache address
tag, and addresses $FF000000 and $00000000 appear different in the MC68EC020
instruction cache. The MC68020, MC68030/EC030, and MC68040/EC040 use all 32 bits
of the address externally. To maintain object-code upgrade compatibility when designing
with the MC68EC020, the upper eight bits should be considered part of the address when
assigning address spaces in hardware.
When enabled, the MC68020/EC020 instruction cache is used to store instruction
prefetches (instruction words and extension words) as they are requested by the CPU.
Instruction prefetches are normally requested from sequential memory addresses except
when a change of program flow occurs (e.g., a branch taken) or when an instruction is
executed that can modify the SR. In these cases, the instruction pipe is automatically
flushed and refilled.
MOTOROLA
M68020 USER’S MANUAL
4- 1