MC68EC020FG25 Freescale Semiconductor, MC68EC020FG25 Datasheet - Page 175

• Manufacturer Part Number: MC68EC020FG25
• Description: IC MPU 32 BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020FG25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

7.2.3.3.2 Protocol. Figure 7-16 shows the protocol for the coprocessor context save
instruction. The main processor initiates execution of the cpSAVE instruction by reading
the save CIR. Thus, the cpSAVE instruction is the only coprocessor instruction that begins
by reading from a CIR. All other coprocessor instructions write to a CIR to initiate
execution of the instruction by the coprocessor. The coprocessor communicates status
information associated with the context save operation to the main processor by placing
coprocessor format codes in the save CIR.
If the coprocessor is not ready to suspend its current operation when the main processor
reads the save CIR, it returns a not-ready format code. The main processor services any
pending interrupts and then reads the save CIR again. After placing the not-ready format
code in the save CIR, the coprocessor should either suspend or complete the instruction it
is currently executing.
Once the coprocessor has suspended or completed the instruction it is executing, it places
a format code representing the internal coprocessor state in the save CIR. When the main
processor reads the save CIR, it transfers the format word to the effective address
specified in the cpSAVE instruction. The lower byte of the coprocessor format word
specifies the number of bytes of state information, not including the format word and
associated null word, to be transferred from the coprocessor to the effective address
specified. If the state information is not a multiple of four bytes in size, the
MC68020/EC020 initiates format error exception processing (refer to 7.5.1.5 Format
Errors). The coprocessor and main processor coordinate the transfer of the internal state
of the coprocessor using the operand CIR. The MC68020/EC020 completes the
coprocessor context save by repeatedly reading the operand CIR and writing the
7-22
M1
OPERATION WORD
M2
M3
1) SERVICE PENDING INTERRUPTS
2) GO TO M2
M4
F-LINE OPWORD AND STORE FORMAT WORD AT
EFFECTIVE ADDRESS
M5
NUMBER OF BYTES INDICATED IN FORMAT WORD
FROM OPERAND CIR TO EFFECTIVE ADDRESS
M6
Figure 7-16. Coprocessor Context Save Instruction Protocol
EVALUATE EFFECTIVE ADDRESS SPECIFIED IN
IF (FORMAT = EMPTY) GO TO M6 ELSE, TRANSFER
RECOGNIZE COPROCESSOR INSTRUCTION F-LINE
READ SAVE CIR TO INITIATE THE cpSAVE INSTRUCTION
IF (FORMAT = NOT READY) DO STEPS 1) AND 2) BELOW
PROCEED WITH EXECUTION OF NEXT INSTRUCTION
MAIN PROCESSOR
M68020 USER’S MANUAL
COPROCESSOR
MOTOROLA