MC68EC020FG25 Freescale Semiconductor, MC68EC020FG25 Datasheet - Page 180

• Manufacturer Part Number: MC68EC020FG25
• Description: IC MPU 32 BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020FG25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

7.3.7 Condition CIR
The main processor initiates a conditional category instruction by writing the condition
selector to bits 5–0 of the 16-bit condition CIR. Bits 15–6 are undefined and reserved by
Motorola. The offset from the base address of the CIR set for the condition CIR is $0E.
Figure 7-20 shows the format of the condition CIR.
7.3.8 Operand CIR
When the coprocessor requests the transfer of an operand, the main processor performs
the transfer by reading from or writing to the 32-bit operand CIR. The offset from the base
address of the CIR set for the operand CIR is $10.
The MC68020/EC020 aligns all operands transferred to and from the operand CIR to the
most significant byte of this CIR. The processor performs a sequence of long-word
transfers to read or write any operand larger than four bytes. If the operand size is not a
multiple of four bytes, the portion remaining after the initial long-word transfer is aligned to
the most significant byte of the operand CIR. Figure 7-21 shows the operand alignment
used by the MC68020/EC020 when accessing the operand CIR.
MOTOROLA
31
BYTE OPERAND
15
TEN-
Figure 7-21. Operand Alignment for Operand CIR Accesses
BYTE-
WORD OPERAND
OPERAND
24
(UNDEFINED, RESERVED)
23
Figure 7-20. Condition CIR Format
THREE-BYTE OPERAND
M68020 USER’S MANUAL
LONG-WORD OPERAND
16
15
NO TRANSFER
6
5
CONDITION SELECTOR
NO TRANSFER
NO TRANSFER
8
7
NO TRANSFER
0
7- 27
0