MC68EC020FG25 Freescale Semiconductor, MC68EC020FG25 Datasheet - Page 196

• Manufacturer Part Number: MC68EC020FG25
• Description: IC MPU 32 BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020FG25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

After reading a valid code from the register select CIR, if DR = 0, the main processor
writes the long-word operand from the specified control register to the operand CIR. If
DR = 1, the main processor reads a long-word operand from the operand CIR and places
it in the specified control register.
7.4.15 Transfer Multiple Main Processor Registers Primitive
The transfer multiple main processor registers primitive transfers long-word operands
between one or more of its data or address registers and the coprocessor. This primitive
applies to general and conditional category instructions. Figure 7-35 shows the format of
the transfer multiple main processor registers primitive.
The transfer multiple main processor registers primitive uses the CA, PC, and DR bits as
described in 7.4.2 Coprocessor Response Primitive General Format. If the
coprocessor issues this primitive with CA = 0 during a conditional category instruction, the
main processor initiates protocol violation exception processing.
When the main processor receives this primitive, it reads a 16-bit register select mask
from the register select CIR. The format of the register select mask is shown in Figure
7-36. A register is transferred if the bit corresponding to the register in the register select
mask is set. The selected registers are transferred in the order D7–D0 and then A7–A0.
If DR = 0, the main processor writes the contents of each register indicated in the register
select mask to the operand CIR using a sequence of long-word transfers. If DR = 1, the
main processor reads a long-word operand from the operand CIR into each register
indicated in the register select mask. The registers are transferred in the same order,
regardless of the direction of transfer indicated by the DR bit.
7.4.16 Transfer Multiple Coprocessor Registers Primitive
The transfer multiple coprocessor registers primitive transfers from 0–16 operands
between the effective address specified in the coprocessor instruction and the
coprocessor. This primitive applies to general category instructions. If the coprocessor
issues this primitive during the execution of a conditional category instruction, the main
processor initiates protocol violation exception processing. Figure 7-37 shows the format
of the transfer multiple coprocessor registers primitive.
MOTOROLA
Figure 7-35. Transfer Multiple Main Processor Registers Primitive Format
15
CA
15
A7
PC
14
14
A6
DR
A5
13
13
Figure 7-36. Register Select Mask Format
12
12
A4
0
11
11
A3
0
10
10
A2
1
M68020 USER’S MANUAL
A1
9
1
9
A0
8
8
0
D7
7
0
7
D6
6
0
6
D5
5
0
5
D4
4
4
0
D3
3
0
3
D2
2
0
2
D1
1
0
1
D0
0
0
0
7- 43