DSPIC30F2020-30I/SP Microchip Technology Inc., DSPIC30F2020-30I/SP Datasheet - Page 114

• Manufacturer Part Number: DSPIC30F2020-30I/SP
• Description: DSP, 16-Bit, 12KB Flash, 512 RAM, 21 I/O, SDIP-28
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F2020-30I/SP

• A/d Inputs: 8-Channels, 10-Bit
• Comparators: 4
• Cpu Speed: 30 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/UART
• Ios: 21
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 28-pin SPDIP
• Programmable Memory: 12K Bytes
• Ram Size: 512 Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC30F1010/202X
REGISTER 12-4:
REGISTER 12-5:
DS70178C-page 112
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
Note 1: The minimum value for this register is 0x0008 and the maximum value is 0xFFEF.
FLTSTAT
HS/HC-0
R/W-0
R/W-0
R/W-0
DTC<1:0>
Master PWM Duty Cycle Value bits
FLTSTAT: Fault Interrupt Status
1 = Fault Interrupt is pending
0 = No Fault Interrupt is pending
This bit is cleared by setting FLTIEN = 0.
CLSTAT: Current-Limit Interrupt Status bit
1 = Current-limit interrupt is pending
0 = No current-limit interrupt is pending
This bit is cleared by setting CLIEN = 0.
TRGSTAT: Trigger Interrupt Status bit
1 = Trigger interrupt is pending
0 = No trigger interrupt is pending
This bit is cleared by setting TRGIEN = 0.
FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt enabled
0 = Fault interrupt disabled and FLTSTAT bit is cleared
HS/HC-0
CLSTAT
Note:
Note:
R/W-0
R/W-0
R/W-0
MDC: PWM MASTER DUTY CYCLE REGISTER
PWMCONx: PWM CONTROL REGISTER
Software must clear the interrupt status here, and the corresponding IFS bit in Interrupt
Controller.
Software must clear the interrupt status here, and the corresponding IFS bit in Interrupt
Controller.
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
TRGSTAT
HS/HC-0
R/W-0
R/W-0
U-0
—
FLTIEN
R/W-0
R/W-0
R/W-0
U-0
Preliminary
—
(1)
MDC<15:8>
MDC<7:0>
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
CLIEN
R/W-0
R/W-0
R/W-0
U-0
—
TRGIEN
R/W-0
R/W-0
R/W-0
U-0
—
© 2006 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
XPRES
R/W-0
R/W-0
R/W-0
R/W-0
ITB
MDCS
R/W-0
R/W-0
R/W-0
R/W-0
IUE
bit 8
bit 0
bit 8
bit 0