DSPIC30F2020-30I/SP Microchip Technology Inc., DSPIC30F2020-30I/SP Datasheet - Page 164

• Manufacturer Part Number: DSPIC30F2020-30I/SP
• Description: DSP, 16-Bit, 12KB Flash, 512 RAM, 21 I/O, SDIP-28
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F2020-30I/SP

• A/d Inputs: 8-Channels, 10-Bit
• Comparators: 4
• Cpu Speed: 30 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/UART
• Ios: 21
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 28-pin SPDIP
• Programmable Memory: 12K Bytes
• Ram Size: 512 Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC30F1010/202X
15.1
The UART module includes a dedicated 16-bit Baud
Rate Generator. The U1BRG register controls the
period of a free-running 16-bit timer. Equation 15-1
shows the formula for computation of the baud rate
with BRGH = 0.
EQUATION 15-1:
Example 15-1 shows the calculation of the baud rate
error for the following conditions:
• F
• Desired Baud Rate = 9600
EXAMPLE 15-1:
DS70178C-page 162
Note 1: Based on T
Desired Baud Rate
Solving for U1BRG value:
Calculated Baud Rate = 7500000/(16 (48 + 1))
Error
Note 1: F
CY
= 7.5 MHz
UART Baud Rate Generator (BRG)
2: Assuming external oscillator with fre-
3: Assuming external oscillator with fre-
U1BRG
U1BRG
U1BRG
Baud Rate =
U1BRG =
frequency (F
quency of 15 MHz and PLL disabled,
F
quency of 15 MHz and PLL enabled,
F
CY
CY
CY
denotes the instruction cycle clock
is 7.5 MHz.
is 30 MHz.
= Fcy/(16 (U1BRG + 1))
= ((F
= ((7500000/9600)/16) – 1
= 48
= 9566
= (Calculated Baud Rate – Desired Baud Rate)
= (9566 – 9600)/9600
= -0.35%
CY
UART BAUD RATE WITH
BRGH = 0
BAUD RATE ERROR CALCULATION (BRGH = 0)
Desired Baud Rate
16 • (U1BRG + 1)
16 • Baud Rate
OSC
= 2/F
CY
/Desired Baud Rate)/16) – 1
/2).
F
F
OSC
CY
CY
(1,2,3)
, PLL are disabled.
– 1
Preliminary
The maximum baud rate (BRGH = 0) possible is
F
possible is F
Equation 15-2 shows the formula for computation of
the baud rate with BRGH = 1.
EQUATION 15-2:
The maximum baud rate (BRGH = 1) possible is F
(for U1BRG = 0) and the minimum baud rate possible
is F
Writing a new value to the U1BRG register causes the
BRG timer to be reset (cleared). This ensures the BRG
does not wait for a timer overflow before generating the
new baud rate.
CY
Note 1: F
CY
/16 (for U1BRG = 0), and the minimum baud rate
/(4 * 65536).
2: Assuming external oscillator with fre-
3: Assuming external oscillator with fre-
Baud Rate =
U1BRG =
CY
frequency.
quency of 15 MHz and PLL disabled,
F
quency of 15 MHz and PLL enabled,
F
CY
CY
CY
/(16 * 65536).
(1)
denotes the instruction cycle clock
is 7.5 MHz.
is 30 MHz.
UART BAUD RATE WITH
BRGH = 1
© 2006 Microchip Technology Inc.
4 • (U1BRG + 1)
4 • Baud Rate
F
F
CY
CY
(1,2,3)
– 1
CY
/4