DSPIC30F2020-30I/SP Microchip Technology Inc., DSPIC30F2020-30I/SP Datasheet - Page 213
DSPIC30F2020-30I/SP
Manufacturer Part Number
DSPIC30F2020-30I/SP
Description
DSP, 16-Bit, 12KB Flash, 512 RAM, 21 I/O, SDIP-28
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F2023-30IPT.pdf
(286 pages)
Specifications of DSPIC30F2020-30I/SP
A/d Inputs
8-Channels, 10-Bit
Comparators
4
Cpu Speed
30 MIPS
Eeprom Memory
0 Bytes
Input Output
21
Interface
I2C/SPI/UART
Ios
21
Memory Type
Flash
Number Of Bits
16
Package Type
28-pin SPDIP
Programmable Memory
12K Bytes
Ram Size
512 Bytes
Timers
3-16-bit, 1-32-bit
Voltage, Range
3-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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18.7.1
A power-on event will generate an internal POR pulse
when a V
at the POR circuit threshold voltage (V
nominally 1.85V. The device supply voltage character-
istics must meet specified starting voltage and rise rate
requirements. The POR pulse will reset a POR timer
and place the device in the Reset state. The POR also
selects the device clock source identified by the
oscillator configuration fuses.
FIGURE 18-8:
FIGURE 18-9:
© 2006 Microchip Technology Inc.
PWRT Time-out
PWRT Time-out
OST Time-out
Internal Reset
OST Time-out
Internal Reset
DD
Internal POR
Internal POR
POR: POWER-ON RESET
rise is detected. The Reset pulse will occur
MCLR
MCLR
V
V
DD
DD
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V
POR
), which is
T
T
OST
OST
Preliminary
T
PWRT
T
PWRT
The POR circuit inserts a small delay, T
nominally 10
circuits are stable. Furthermore, a user selected power-
up time-out (T
is based on Configuration bits and can be 0 ms (no
delay), 4 ms, 16 ms or 64 ms. The total delay is at
device power-up T
have expired, SYSRST will be negated on the next
leading edge of the Q1 clock, and the PC will jump to
the Reset vector.
The timing for the SYSRST signal is shown in
Figure 18-8 through Figure 18-10.
dsPIC30F1010/202X
PWRT
s and ensures that the device bias
POR
) is applied. The T
+ T
DD
PWRT
)
. When these delays
DD
DS70178C-page 211
): CASE 1
PWRT
POR
parameter
, which is
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