DSPIC30F2020-30I/SP Microchip Technology Inc., DSPIC30F2020-30I/SP Datasheet - Page 174

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DSPIC30F2020-30I/SP

Manufacturer Part Number
DSPIC30F2020-30I/SP
Description
DSP, 16-Bit, 12KB Flash, 512 RAM, 21 I/O, SDIP-28
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet

Specifications of DSPIC30F2020-30I/SP

A/d Inputs
8-Channels, 10-Bit
Comparators
4
Cpu Speed
30 MIPS
Eeprom Memory
0 Bytes
Input Output
21
Interface
I2C/SPI/UART
Ios
21
Memory Type
Flash
Number Of Bits
16
Package Type
28-pin SPDIP
Programmable Memory
12K Bytes
Ram Size
512 Bytes
Timers
3-16-bit, 1-32-bit
Voltage, Range
3-5.5
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device
dsPIC30F1010/202X
REGISTER 16-1:
DS70178C-page 172
bit 2-0
ADCS<2:0>: A/D Conversion Clock Divider Select bits
If PLL is enabled (assume 15 MHz external clock as clock source):
111 = F
110 = F
101 = F
100 = F
011 = F
010 = F
001 = F
000 = F
If PLL is disabled (assume 15 MHz external clock as clock source):
111 = F
110 = F
101 = F
100 = F
011 = F
010 = F
001 = F
000 = F
Note:
A/D CONTROL REGISTER (ADCON) (CONTINUED)
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
/18 = 13.3 MHz @ 30 MIPS
/16 = 15.0 MHz @ 30 MIPS
/14 = 17.1 MHz @ 30 MIPS
/12 = 20.0 MHz @ 30 MIPS
/10 = 24.0 MHz @ 30 MIPS
/8 = 30.0 MHz @ 30 MIPS
/6 = Reserved, defaults to 30 MHz @ 30 MIPS
/4 = Reserved, defaults to 30 MHz @ 30 MIPS
/18 = 0.83 MHz @ 7.5 MIPS
/16 = 0.93 MHz @ 7.5 MIPS
/14 = 1.07 MHz @ 7.5 MIPS
/12 = 1.25 MHz @ 7.5 MIPS
/10 = 1.5 MHz @ 7.5 MIPS
/8 = 1.87 MHz @ 7.5 MIPS
/6 = 2.5 MHz @ 7.5 MIPS
/4 = 3.75 MHz @ 7.5 MIPS
See Figure 18-2 for ADC clock derivation.
Preliminary
© 2006 Microchip Technology Inc.

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