PIC24FJ256DA210-I/PT Microchip Technology Inc., PIC24FJ256DA210-I/PT Datasheet - Page 141

• Manufacturer Part Number: PIC24FJ256DA210-I/PT
• Description: 100 TQFP 12x12x1mm TRAY, 16-bit, 256KB Flash, 96K RAM, USB, Graphics
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256DA210-I/PT

• A/d Inputs: 24 Channel, 10-Bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 84
• Interface: I2C/SPI/UART
• Memory Capacity: 256 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Leads: 100
• Number Of Pins: 100
• Package Type: 100-Pin TQFP
• Programmable Memory: 256K Bytes
• Ram Size: 96K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to +85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Voltage, Rating: 2.2-3.6 V
• Run Mode: 800 μA/MIPS, 3.3 V Typical
• Standby Current With 32 Khz Oscillator: 22 μA, 3.3 V Typical
• Lead Free Status / Rohs Status: RoHS Compliant part

8.0
The oscillator system for PIC24FJ256DA210 family
devices has the following features:
• A total of four external and internal oscillator options
FIGURE 8-1:
 2010 Microchip Technology Inc.
Note:
as clock sources, providing 11 different clock modes
Note 1:
SOSCO
SOSCI
OSCO
OSCI
OSCILLATOR
CONFIGURATION
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
Section 6. “Oscillator” (DS39700). The
information in this data sheet supersedes
the information in the FRM.
Refer to Figure 8-2 for more information on the 96 MHz PLL block.
Primary Oscillator
Oscillator
Oscillator
Secondary Oscillator
Family
PIC24FJ256DA210 FAMILY CLOCK DIAGRAM
LPRC
FRC
(nominal)
SOSCEN
Enable
Oscillator
8 MHz
Reference
31 kHz (nominal)
96 MHz PLL
PLLDIV<2:0>
Manual”,
PIC24FJ256DA210 FAMILY
CLKDIV<10:8>
(1)
PLL and
DIV
1/16
GCLKDIV<6:0>
CPDIV<1:0>
PIC24FJ256DA210 Family
8 MHz/
4 MHz
• An on-chip PLL block to boost internal operating
• Software controllable switching between various
• Software controllable postscaler for selective
• A Fail-Safe Clock Monitor (FSCM) that detects
• A separate and independently configurable system
A simplified diagram of the oscillator system is shown
in Figure 8-1.
ECPLL,FRCPLL
XTPLL, HSPLL
frequency on select internal and external oscillator
sources, and to provide a precise clock source for
peripherals, such as USB and graphics
clock sources
clocking of CPU for system power savings
clock failure and permits safe application recovery
or shutdown
clock output for synchronizing external hardware
XT, HS, EC
48/96 MHz Clock for Graphics Controller Module
FRCDIV
LPFRC
SOSC
LPRC
Clock Control Logic
FRC
Fail-Safe
Monitor
Clock
CLKDIV<14:12>
Clock for Display Interface
Reference Clock
Clock Source Option
Generator
48 MHz USB Clock
REFOCON<15:8>
for Other Modules
DS39969B-page 141
Peripherals
WDT
REFO
CLKO
CPU