PIC24FJ256DA210-I/PT Microchip Technology Inc., PIC24FJ256DA210-I/PT Datasheet - Page 45

• Manufacturer Part Number: PIC24FJ256DA210-I/PT
• Description: 100 TQFP 12x12x1mm TRAY, 16-bit, 256KB Flash, 96K RAM, USB, Graphics
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256DA210-I/PT

• A/d Inputs: 24 Channel, 10-Bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 84
• Interface: I2C/SPI/UART
• Memory Capacity: 256 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Leads: 100
• Number Of Pins: 100
• Package Type: 100-Pin TQFP
• Programmable Memory: 256K Bytes
• Ram Size: 96K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to +85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Voltage, Rating: 2.2-3.6 V
• Run Mode: 800 μA/MIPS, 3.3 V Typical
• Standby Current With 32 Khz Oscillator: 22 μA, 3.3 V Typical
• Lead Free Status / Rohs Status: RoHS Compliant part

4.0
As Harvard architecture devices, PIC24F micro-
controllers feature separate program and data memory
spaces and busses. This architecture also allows direct
access of program memory from the data space during
code execution.
4.1
The
PIC24FJ256DA210 family devices is 4M instructions.
The space is addressable by a 24-bit value derived
FIGURE 4-1:
 2010 Microchip Technology Inc.
program
Note:
MEMORY ORGANIZATION
Program Memory Space
Memory areas are not shown to scale.
address
PROGRAM SPACE MEMORY MAP FOR PIC24FJ256DA210 FAMILY DEVICES
memory
space
PIC24FJ128DAXXX
Device Config Registers
Alternate Vector Table
Interrupt Vector Table
Flash Config Words
(44K instructions)
Program Memory
GOTO Instruction
Unimplemented
Reset Address
User Flash
DEVID (2)
Reserved
Reserved
Reserved
of
Read ‘0’
PIC24FJ256DA210 FAMILY
the
from either the 23-bit Program Counter (PC) during pro-
gram execution, or from table operation or data space
remapping, as described in Section 4.3 “Interfacing
Program and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the PIC24FJ256DA210 family of
devices are shown in Figure 4-1.
Device Config Registers
PIC24FJ256DAXXX
Alternate Vector Table
Interrupt Vector Table
Flash Config Words
Program Memory
(87K instructions)
GOTO Instruction
Unimplemented
Reset Address
User Flash
DEVID (2)
Reserved
Reserved
Reserved
Read ‘0’
000000h
000002h
000004h
0000FEh
000100h
000104h
0001FEh
000200h
0157FEh
015800h
02ABFEh
02AC00h
7FFFFEh
800000h
F7FFFEh
F80000h
F8000Eh
F80010h
FEFFFEh
FF0000h
FFFFFEh
DS39969B-page 45