PIC24FJ256DA210-I/PT Microchip Technology Inc., PIC24FJ256DA210-I/PT Datasheet - Page 317

• Manufacturer Part Number: PIC24FJ256DA210-I/PT
• Description: 100 TQFP 12x12x1mm TRAY, 16-bit, 256KB Flash, 96K RAM, USB, Graphics
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256DA210-I/PT

• A/d Inputs: 24 Channel, 10-Bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 84
• Interface: I2C/SPI/UART
• Memory Capacity: 256 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Leads: 100
• Number Of Pins: 100
• Package Type: 100-Pin TQFP
• Programmable Memory: 256K Bytes
• Ram Size: 96K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to +85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Voltage, Rating: 2.2-3.6 V
• Run Mode: 800 μA/MIPS, 3.3 V Typical
• Standby Current With 32 Khz Oscillator: 22 μA, 3.3 V Typical
• Lead Free Status / Rohs Status: RoHS Compliant part

REGISTER 22-21: G1ACTDA: ACTIVE DISPLAY AREA REGISTER
REGISTER 22-22: G1HSYNC: HORIZONTAL SYNCHRONIZATION CONTROL REGISTER
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7-0
ACTLINE7
ACTPIX7
HSLEN7
HSST7
R/W-0
R/W-0
R/W-0
R/W-0
HSLEN<7:0>: HSYNC Pulse-Width Configuration bits (in DISPCLKs)
DPHSOE bit (G1CON3<0>) must be set for the HSYNC signal to toggle; minimum value is 1.
HSST<7:0>: HSYNC Start Delay Configuration bits (in DISPCLKs)
This is the number of DISPCLK cycles from the start of horizontal blanking to the start of HSYNC active.
ACTLINE<7:0>: Number of Lines Before the First Active (Displayed) Line bits
Typically, ACTLINEx = VENSTx (G1DBLCON<15:8>).
This register is added for versatility in the timing of the active lines.
For TFT mode, DPMODE bits (G1CON2<2:0>) = 001; the minimum value is 2.
For STN mode, DPMODE bits (G1CON2<2:0>) = 010,011,100; the minimum value is 0.
ACTPIX<7:0>: Number of Pixels Before the First Active (Displayed) Pixel bits (in DISPCLKs)
Typically, ACTPIXx = HENSTx (G1DBLCON<7:0>).
This register is added for versatility in the timing of the active pixels. Note that the programmed value
is computed in DISPCLK cycles. This value is dependent on the DPGWDTH bit (G1CON2<15:14>).
Refer to the “PIC24F Family Reference Manual”, Section 43. “Graphics Controller Module (GFX)”
for details.
ACTLINE6
HSLEN6
ACTPIX6
HSST6
R/W-0
R/W-0
R/W-0
R/W-0
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
ACTLINE5
HSLEN5
ACTPIX5
HSST5
R/W-0
R/W-0
R/W-0
R/W-0
HSLEN4
PIC24FJ256DA210 FAMILY
ACTLINE4
HSST4
R/W-0
R/W-0
ACTPIX4
R/W-0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
HSLEN3
HSST3
R/W-0
R/W-0
ACTLINE3
ACTPIX3
R/W-0
R/W-0
HSLEN2
HSST2
R/W-0
R/W-0
ACTLINE2
ACTPIX2
R/W-0
R/W-0
x = Bit is unknown
HSLEN1
x = Bit is unknown
HSST1
ACTLINE1
R/W-0
R/W-0
ACTPIX1
R/W-0
R/W-0
DS39969B-page 317
ACTLINE0
HSLEN0
ACTPIX0
HSST0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
bit 0
bit 8
bit 0