PIC24FJ256DA210-I/PT Microchip Technology Inc., PIC24FJ256DA210-I/PT Datasheet - Page 306

• Manufacturer Part Number: PIC24FJ256DA210-I/PT
• Description: 100 TQFP 12x12x1mm TRAY, 16-bit, 256KB Flash, 96K RAM, USB, Graphics
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256DA210-I/PT

• A/d Inputs: 24 Channel, 10-Bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 84
• Interface: I2C/SPI/UART
• Memory Capacity: 256 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Leads: 100
• Number Of Pins: 100
• Package Type: 100-Pin TQFP
• Programmable Memory: 256K Bytes
• Ram Size: 96K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to +85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Voltage, Rating: 2.2-3.6 V
• Run Mode: 800 μA/MIPS, 3.3 V Typical
• Standby Current With 32 Khz Oscillator: 22 μA, 3.3 V Typical
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC24FJ256DA210 FAMILY
22.1
REGISTER 22-1:
REGISTER 22-2:
DS39969B-page 306
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
GCMD15
GCMD31
GCMD23
GCMD7
R/W-0
R/W-0
R/W-0
R/W-0
GFX Module Registers
GCMD<15:0>: Low GPU Command bits
The full 32-bit command is defined by G1CMDH and G1CMDL (GCMD<31:0>). Writes to this register
will not trigger the loading of GCMD <31:0> to the command FIFO. For command FIFO loading, see
the G1CMDH register description.
GCMD<31:16>: High GPU Command bits
The full 32-bit command is defined by G1CMDH and G1CMDL (GCMD<31:0>). A word write to the
G1CMDH register triggers the loading of GCMD<31:0> to the command FIFO. Byte writes to the
G1CMDH are allowed but only a high byte write will trigger the command loading to the FIFO. Low
byte write to this register will only update the G1CMDH<7:0> bits.
GCMD14
GCMD30
GCMD22
GCMD6
R/W-0
R/W-0
R/W-0
R/W-0
G1CMDL: GPU COMMAND LOW REGISTER
G1CMDH: GPU COMMAND HIGH REGISTER
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
GCMD13
GCMD29
GCMD21
GCMD5
R/W-0
R/W-0
R/W-0
R/W-0
GCMD12
GCMD28
GCMD20
GCMD4
R/W-0
R/W-0
R/W-0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
GCMD27
GCMD19
GCMD11
GCMD3
R/W-0
R/W-0
R/W-0
R/W-0
GCMD10
GCMD26
GCMD18
GCMD2
R/W-0
R/W-0
R/W-0
R/W-0
 2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
GCMD25
GCMD17
GCMD9
GCMD1
R/W-0
R/W-0
R/W-0
R/W-0
GCMD24
GCMD16
GCMD8
GCMD0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
bit 0
bit 8
bit 0