PIC24FJ256DA210-I/PT Microchip Technology Inc., PIC24FJ256DA210-I/PT Datasheet - Page 69

• Manufacturer Part Number: PIC24FJ256DA210-I/PT
• Description: 100 TQFP 12x12x1mm TRAY, 16-bit, 256KB Flash, 96K RAM, USB, Graphics
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256DA210-I/PT

• A/d Inputs: 24 Channel, 10-Bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 84
• Interface: I2C/SPI/UART
• Memory Capacity: 256 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Leads: 100
• Number Of Pins: 100
• Package Type: 100-Pin TQFP
• Programmable Memory: 256K Bytes
• Ram Size: 96K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to +85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Voltage, Rating: 2.2-3.6 V
• Run Mode: 800 μA/MIPS, 3.3 V Typical
• Standby Current With 32 Khz Oscillator: 22 μA, 3.3 V Typical
• Lead Free Status / Rohs Status: RoHS Compliant part

TABLE 4-31:
G1CMDL
G1CMDH
G1CON1
G1STAT
G1IE
G1IR
G1W1ADRL
G1W1ADRH
G1W2ADRL
G1W2ADRH
G1PUW
G1PUH
G1DPADRL
G1DPADRH
G1DPW
G1DPH
G1DPWT
G1DPHT
G1CON2
G1CON3
G1ACTDA
G1HSYNC
G1VSYNC
G1DBLCON
G1CLUT
G1CLUTWR
G1CLUTRD
G1MRGN
G1CHRX
G1CHRY
G1IPU
G1DBEN
Legend:
File Name
Addr
070A
070C
070E
071A
071C
071E
072A
072C
072E
073C
0700
0702
0704
0706
0708
0710
0712
0714
0716
0718
0720
0722
0724
0726
0728
0730
0732
0734
0736
0738
073A
073E
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DPGWDTH1 DPGWDTH0 DPSTGER1 DPSTGER0
GDBEN15
PUBUSY
CLUTEN
Bit 15
G1EN
GRAPHICS REGISTER MAP
PUIE
PUIF
—
—
—
—
—
—
—
—
—
—
—
—
—
CLUTBUSY
GDBEN14
Bit 14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Vertical Blanking Start to First Displayed Line Configuration Regsiter
GDBEN13
G1SIDL
Bit 13
Number of Lines Before the First Active Line Register
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
HSYNC Pulse-Width Configuration Register
VSYNC Pulse-Width Configuration Register
Vertical Blanking Advance Register
GCMDWMK4 GCMDWMK3 GCMDWMK2 GCMDWMK1 GCMDWMK0
GDBEN12
Bit 12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GDBEN11
Bit 11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GDBEN10
Bit 10
—
—
—
—
—
—
—
—
—
—
Color Look-up Table Memory Write Data Register
Color Look-up Table Memory Read Data Register
DPTEST1
DPPINOE
CLUTTRD
GPU Work Area 1 Start Address Register<15:0>
GPU Work Area 2 Start Address Register<15:0>
GDBEN9
Display Buffer Start Address Register<15:0>
Bit 9
—
—
—
—
—
—
—
Graphics Command Register<31:16>
Graphics Command Register<15:0>
CLUTRWEN
DPPOWER DPCLKPOL DPENPOL DPVSPOL DPHSPOL
DPTEST0
GDBEN8
Bit 8
—
—
—
—
—
—
—
IPUBUSY
DPBPP2
GDBEN7
PUBPP2
IPUIE
IPUIF
Bit 7
—
Current Character X-Coordinate Position Register
Current Character Y-Coordinate Position Register
RCCBUSY CHRBUSY
DPBPP1
GDBEN6
PUBPP1
RCCIE
GPU Work Area Height Register
RCCIF
GPU Work Area Width Register
Bit 6
Display Frame Height Register
Display Frame Width Register
Display Total Height Register
Display Total Width Register
—
Horizontal Blanking Start to First Displayed Line Configuration Regsiter
HUFFERR BLCKERR
Number of Pixels Before the First Active PIxel Register
GDBEN5
DPBPP0
PUBPP0
CHRIE
CHRIF
Bit 5
GPU Work Area 1 Start Address Register<23:16>
GPU Work Area 2 Start Address Register<23:16>
Color Look-Up Table Memory Address Register
Display Buffer Start Address Register<23:16>
HSYNC Start Delay Configuration Register
VSYNC Start Delay Configuration Register
Horizontal Blanking Advance Register
GCMDCNT4 GCMDCNT3 GCMDCNT2 GCMDCNT1 GCMDCNT0
VMRGNIE
VMRGNIF
GDBEN4
VMRGN
Bit 4
—
DPPWROE
HMRGNIE
HMRGNIF
LENERR
GDBEN3
HMRGN
Bit 3
—
WRAPERR
DPMODE2
CMDLVIE
CMDLVIF
DPENOE
GDBEN2
CMDLV
Bit 2
CMDFULIE CMDMPTIE
CMDFULIF CMDMPTIF
DPMODE1 DPMODE0
IPUDONE
CMDFUL
DPVSOE
GDBEN1
Bit 1
CMDMPT
DPHSOE
GDBEN0
BFINAL
Bit 0
Resets
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
All