PIC24FJ256DA210-I/PT Microchip Technology Inc., PIC24FJ256DA210-I/PT Datasheet - Page 147

• Manufacturer Part Number: PIC24FJ256DA210-I/PT
• Description: 100 TQFP 12x12x1mm TRAY, 16-bit, 256KB Flash, 96K RAM, USB, Graphics
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256DA210-I/PT

• A/d Inputs: 24 Channel, 10-Bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 84
• Interface: I2C/SPI/UART
• Memory Capacity: 256 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Leads: 100
• Number Of Pins: 100
• Package Type: 100-Pin TQFP
• Programmable Memory: 256K Bytes
• Ram Size: 96K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to +85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Voltage, Rating: 2.2-3.6 V
• Run Mode: 800 μA/MIPS, 3.3 V Typical
• Standby Current With 32 Khz Oscillator: 22 μA, 3.3 V Typical
• Lead Free Status / Rohs Status: RoHS Compliant part

REGISTER 8-4:
 2010 Microchip Technology Inc.
GCLKDIV6
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at all Resets
bit 15-9
bit 8-0
Note 1:
R/W-0
U-0
—
These bits take effect only when the 96 MHz PLL is enabled.
(1)
GCLKDIV5
GCLKDIV<6:0>: Display Module Interface Clock Divider Selection bits
(Values are based on a 96 MHz clock source set by G1CLKSEL (CLKDIV<4>) = 1. When the 48 MHz
clock source is selected, G1CLKSEL (CLKDIV<4>) = 0; all values are divided by 2.)
1111111 = (127) 1.50 MHz (divide by 64)
1111110 = (126) 1.52 MHz (divide by 63)
·
·
·
1100001 = (97) 2.82 MHz (divide by 34)
1100000 = (96) 2.91 MHz (divide by 33); from here, increment the divisor by 1.00
1011111 = (95) 2.95 MHz (divide by 32.50)
·
·
·
1000000 = (65) 5.49 MHz (divide by 17.50)
1000000 = (64) 5.65 MHz (divide by 17.00); from here, increment the divisor by 0.50
0111111 = (63) 5.73 MHz (divide by 16.75)
·
·
·
0000011 = (3) 54.86 MHz (divide by 1.75)
0000010 = (2) 64.00 MHz (divide by 1.5)
0000001 = (1) 76.80 MHz (divide by 1.25); from here, increment the divisor by 0.25
0000000 = (0) 96.00 MHz (divide by 1)
Unimplemented: Read as ‘0’
R/W-0
U-0
—
CLKDIV2: CLOCK DIVIDER REGISTER 2
(1)
GCLKDIV4
W = Writable bit
‘1’ = Bit is set
R/W-0
U-0
—
(1)
GCLKDIV3
PIC24FJ256DA210 FAMILY
R/W-0
U-0
—
(1)
U = Unimplemented bit, read as ‘0’
GCLKDIV2
‘0’ = Bit is cleared
R/W-0
U-0
—
(1)
GCLKDIV1
R/W-0
U-0
—
(1)
(1)
GCLKDIV0
x = Bit is unknown
R/W-0
U-0
—
DS39969B-page 147
(1)
(1)
U-0
U-0
—
—
bit 8
bit 0