PIC24FJ256GB206-I/MR Microchip Technology Inc., PIC24FJ256GB206-I/MR Datasheet - Page 141

• Manufacturer Part Number: PIC24FJ256GB206-I/MR
• Description: 16-bit, 256KB Flash, 96K RAM, USB, 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB206-I/MR

• A/d Inputs: 16 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin QFN
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 8-2:
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-12
bit 11
bit 10-8
bit 7-6
bit 5
bit 4
bit 3-0
Note 1:
CPDIV1
R/W-0
R/W-0
ROI
2:
This bit is automatically cleared when the ROI bit is set and an interrupt occurs.
This setting is not allowed while the USB module is enabled.
ROI: Recover on Interrupt bit
1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1
0 = Interrupts have no effect on the DOZEN bit
DOZE<2:0>: CPU Peripheral Clock Ratio Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
DOZEN: DOZE Enable bit
1 = DOZE<2:0> bits specify the CPU peripheral clock ratio
0 = CPU peripheral clock ratio is set to 1:1
RCDIV<2:0>: FRC Postscaler Select bits
111 = 31.25 kHz (divide-by-256)
110 = 125 kHz (divide-by-64)
101 = 250 kHz (divide-by-32)
100 = 500 kHz (divide-by-16)
011 = 1 MHz (divide-by-8)
010 = 2 MHz (divide-by-4)
001 = 4 MHz (divide-by-2)
000 = 8 MHz (divide-by-1)
CPDIV<1:0>: System Clock Select bits (postscaler select from 32 MHz clock branch)
11 = 4 MHz (divide-by-8)
10 = 8 MHz (divide-by-4)
01 = 16 MHz (divide-by-2)
00 = 32 MHz (divide-by-1)
PLLEN: 96 MHz PLL Enable bit
The 96 MHz PLL must be enabled when the USB module is enabled. This control bit can be overridden
by the PLL96MHZ (Configuration Word 2 <11>) Configuration bit.
1 = Enable the 96 MHz PLL for USB or HSPLL/ECPLL/FRCPLL operation
0 = Disable the 96 MHz PLL
Reserved: Reserved bit; do not use
Unimplemented: Read as ‘0’
CPDIV0
DOZE2
R/W-0
R/W-0
CLKDIV: CLOCK DIVIDER REGISTER
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
DOZE1
PLLEN
R/W-0
R/W-0
(2)
(2)
(1)
Reserved
PIC24FJ256GB210 FAMILY
DOZE0
R/W-0
r-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
DOZEN
R/W-0
U-0
—
(1)
RCDIV2
R/W-0
U-0
—
x = Bit is unknown
RCDIV1
R/W-0
U-0
—
DS39975A-page 141
RCDIV0
R/W-1
U-0
—
bit 8
bit 0