PIC24FJ256GB206-I/MR Microchip Technology Inc., PIC24FJ256GB206-I/MR Datasheet - Page 219

• Manufacturer Part Number: PIC24FJ256GB206-I/MR
• Description: 16-bit, 256KB Flash, 96K RAM, USB, 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB206-I/MR

• A/d Inputs: 16 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin QFN
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

16.2
To compute the Baud Rate Generator reload value, use
Equation 16-1.
EQUATION 16-1:
TABLE 16-1:
TABLE 16-2:
 2010 Microchip Technology Inc.
Note 1:
Note 1:
Note 1: Based on F
Required System F
Slave Address
0000 000
0000 000
0000 001
0000 01x
0000 1xx
1111 0xx
1111 1xx
or:
I2CxBRG =
2: These clock rate values are for guidance
2:
2:
3:
Setting Baud Rate When
Operating as a Bus Master
100 kHz
100 kHz
100 kHz
400 kHz
400 kHz
400 kHz
400 kHz
1 MHz
1 MHz
1 MHz
PLL are disabled.
only. The actual clock rate can be affected
by various system level parameters. The
actual clock rate should be measured in
its intended application.
Based on F
These clock rate values are for guidance only. The actual clock rate can be affected by various system
level parameters. The actual clock rate should be measured in its intended application.
The address bits listed here will never cause an address match, independent of address mask settings.
The address will be Acknowledged only if GCEN = 1.
A match on this address can only occur on the upper byte in 10-Bit Addressing mode.
FSCL =
I
I
(
2
2
C™ CLOCK RATES(1,2)
C™ RESERVED ADDRESSES
R/W Bit
I2CxBRG + 1 +
SCL
FSCL
CY
COMPUTING BAUD RATE
RELOAD VALUE
F
CY
0
1
x
x
x
x
x
CY
= F
= F
OSC
OSC
General Call Address
Start Byte
CBus Address
Reserved
HS Mode Master Code
10-Bit Slave Upper Byte
Reserved
–
F
/2; Doze mode and
16 MHz
16 MHz
16 MHz
CY
8 MHz
4 MHz
8 MHz
4 MHz
2 MHz
8 MHz
4 MHz
/2; Doze mode and PLL are disabled.
10,000,000
F
CY
10,000,000
F
CY
F
CY
(1,2)
– 1
PIC24FJ256GB210 FAMILY
)
(Decimal)
(2)
157
78
39
37
18
13
(1)
(3)
9
4
6
3
I2CxBRG Value
16.3
The I2CxMSK register (Register 16-3) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit loca-
tion (= 1) in the I2CxMSK register causes the slave
module to respond whether the corresponding address
bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK
is set to ‘00100000’, the slave module will detect both
addresses, ‘0000000’ and ‘0100000’.
To enable address masking, the Intelligent Peripheral
Management Interface (IPMI) must be disabled by
clearing the IPMIEN bit (I2CxCON<11>).
Note:
Description
(Hexadecimal)
Slave Address Masking
9D
As a result of changes in the I
col, the addresses in Table 16-2 are
reserved and will not be Acknowledged in
Slave mode. This includes any address
mask settings that include any of these
addresses.
4E
27
25
12
D
9
4
6
3
Actual F
1.026 MHz
1.026 MHz
0.909 MHz
100 kHz
100 kHz
404 kHz
404 kHz
385 kHz
385 kHz
99 kHz
DS39975A-page 219
SCL
2
C™ proto-