PIC24FJ256GB206-I/MR Microchip Technology Inc., PIC24FJ256GB206-I/MR Datasheet - Page 202

• Manufacturer Part Number: PIC24FJ256GB206-I/MR
• Description: 16-bit, 256KB Flash, 96K RAM, USB, 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB206-I/MR

• A/d Inputs: 16 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin QFN
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC24FJ256GB210 FAMILY
REGISTER 14-2:
DS39975A-page 202
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10-9
bit 8
bit 7
bit 6
bit 5
Note 1:
OCTRIG
FLTMD
R/W-0
R/W-0
2:
3:
Never use an OC module as its own trigger source, either by selecting this mode or another equivalent
SYNCSEL setting.
Use these inputs as trigger sources only and never as sync sources.
The DCB<1:0> bits are double-buffered in the PWM modes only (OCM<2:0> (OCxCON1<2:0>) = 111, 110).
FLTMD: Fault Mode Select bit
1 = Fault mode is maintained until the Fault source is removed and the corresponding OCFLT0 bit is
0 = Fault mode is maintained until the Fault source is removed and a new PWM period starts
FLTOUT: Fault Out bit
1 = PWM output is driven high on a Fault
0 = PWM output is driven low on a Fault
FLTTRIEN: Fault Output State Select bit
1 = Pin is forced to an output on a Fault condition
0 = Pin I/O condition is unaffected by a Fault
OCINV: OCMP Invert bit
1 = OCx output is inverted
0 = OCx output is not inverted
Unimplemented: Read as ‘0’
DCB<11:0>: PWM Duty Cycle Least Significant bits
11 = Delay OCx falling edge by ¾ of the instruction cycle
10 = Delay OCx falling edge by ½ of the instruction cycle
01 = Delay OCx falling edge by ¼ of the instruction cycle
00 = OCx falling edge occurs at the start of the instruction cycle
OC32: Cascade Two OC Modules Enable bit (32-bit operation)
1 = Cascade module operation is enabled
0 = Cascade module operation is disabled
OCTRIG: OCx Trigger/Sync Select bit
1 = Trigger OCx from the source designated by the SYNCSELx bits
0 = Synchronize OCx with the source designated by the SYNCSELx bits
TRIGSTAT: Timer Trigger Status bit
1 = Timer source has been triggered and is running
0 = Timer source has not been triggered and is being held clear
OCTRIS: OCx Output Pin Direction Select bit
1 = OCx pin is tri-stated
0 = Output compare peripheral x is connected to an OCx pin
TRIGSTAT
R/W-0 HS
FLTOUT
R/W-0
cleared in software
OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2
HS = Hardware Settable bit
W = Writable bit
‘1’ = Bit is set
FLTTRIEN
OCTRIS
R/W-0
R/W-0
SYNCSEL4
OCINV
R/W-0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SYNCSEL3
R/W-1
U-0
—
(3)
SYNCSEL2
DCB1
R/W-0
R/W-1
(3)
 2010 Microchip Technology Inc.
x = Bit is unknown
SYNCSEL1
DCB0
R/W-0
R/W-0
(3)
SYNCSEL0
R/W-0
R/W-0
OC32
bit 8
bit 0