PIC24FJ256GB206-I/MR Microchip Technology Inc., PIC24FJ256GB206-I/MR Datasheet - Page 68

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PIC24FJ256GB206-I/MR

Manufacturer Part Number
PIC24FJ256GB206-I/MR
Description
16-bit, 256KB Flash, 96K RAM, USB, 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC24FJ256GB206-I/MR

A/d Inputs
16 Channel, 10-bit
Comparators
3
Cpu Speed
16 MIPS
Eeprom Memory
0 Bytes
Input Output
52
Interface
I2C/SPI/UART/USART/USB
Memory Type
Flash
Number Of Bits
16
Package Type
64-pin QFN
Programmable Memory
256K Bytes
Ram Size
98K Bytes
Speed
32 MHz
Temperature Range
–40 to 85 °C
Timers
5-16-bit
Voltage, Range
2.2-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device
PIC24FJ256GB210 FAMILY
4.2.5
The
PIC24FJ256GB210
accomplished by a new technique, called the Extended
Data Space (EDS).
The EDS includes any additional internal extended
data memory not accessible by the lower 32 Kbytes of
data address space, any external memory through
EPMP and the Program Space Visibility (PSV).
The extended data space is always accessed through
the EDS window, which is the upper half of data space.
The entire extended data space is organized into EDS
FIGURE 4-4:
DS39975A-page 68
enhancement
EXTENDED DATA SPACE (EDS)
30 KB Data
32 KB EDS
Registers
Memory
Function
Window
Special
0x0800
0x8000
0x0000
0xFFFE
EXTENDED DATA SPACE
family
of
the
0x00FFFE
0x008000
Extended
DSxPAG
= 0x001
Extended SRAM (66 KB)
Internal
Memory
devices
data
EPMP Memory Space
0x0187FE
0x018000
0x01FFFE
Extended
0x018800
DSxPAG
= 0x003
External
Internal
Memory
Memory
has
Access
EPMP
space
using
been
in
0xFF8000
0xFFFFFE
DSx PAG
= 0x1FF
External
Memory
Access
EPMP
using
pages, each having 32 Kbytes of data. Mapping of the
EDS page into the EDS window is done by using the
Data Space Read register (DSRPAG<9:0>) for read
operations
(DSWPAG<8:0>) for write operations. Figure 4-4
displays the entire EDS space.
EDS Space
0x000000
0x007FFE
DSRPAG
= 0x200
Note:
Program
Access
Space
Accessing Page 0 in the EDS window will
generate an address error trap as Page 0
is the base data memory (data locations,
0x0800 to 0x7FFF, in the lower data
space).
0x7FFFFE
0x7F8000
DSRPAG
= 0x2FF
and
Program
Access
Space
Program Memory
Data
 2010 Microchip Technology Inc.
0x000001
DSRPAG
= 0x300
0x007FFF
Program
Access
Space
Space
0x7FFFFF
DSRPAG
= 0x3FF
0x7F8001
Program
Access
Space
Write
register

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