PIC24FJ256GB206-I/MR Microchip Technology Inc., PIC24FJ256GB206-I/MR Datasheet - Page 144

• Manufacturer Part Number: PIC24FJ256GB206-I/MR
• Description: 16-bit, 256KB Flash, 96K RAM, USB, 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB206-I/MR

• A/d Inputs: 16 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin QFN
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC24FJ256GB210 FAMILY
A recommended code sequence for a clock switch
includes the following:
1.
2.
3.
4.
5.
6.
7.
8.
The core sequence for unlocking the OSCCON register
and initiating a clock switch is shown in Example 8-1.
EXAMPLE 8-1:
DS39975A-page 144
;Place the new oscillator selection in W0
;OSCCONH (high byte) Unlock Sequence
MOV
MOV
MOV
MOV.b
MOV.b
;Set new oscillator selection
MOV.b
;OSCCONL (low byte) unlock sequence
MOV
MOV
MOV
MOV.b
MOV.b
;Start oscillator switch operation
BSET
Disable interrupts during the OSCCON register
unlock and write sequence.
Execute the unlock sequence for the OSCCON
high
OSCCON<15:8> in two back-to-back instructions.
Write new oscillator source to the NOSCx bits in
the instruction immediately following the unlock
sequence.
Execute the unlock sequence for the OSCCON
low
OSCCON<7:0> in two back-to-back instructions.
Set the OSWEN bit in the instruction immediately
following the unlock sequence.
Continue
clock-sensitive (optional).
Invoke an appropriate amount of software delay
(cycle counting) to allow the selected oscillator
and/or PLL to start and stabilize.
Check to see if OSWEN is ‘0’. If it is, the switch
was successful. If OSWEN is still set, then check
the LOCK bit to determine the cause of failure.
byte
byte
#OSCCONH, w1
#0x78, w2
#0x9A, w3
w2, [w1]
w3, [w1]
WREG, OSCCONH
#OSCCONL, w1
#0x46, w2
#0x57, w3
w2, [w1]
w3, [w1]
OSCCON,#0
to
by
by
execute
writing
writing
BASIC CODE SEQUENCE
FOR CLOCK SWITCHING
IN ASSEMBLY
code
46h
78h
and
and
that
9Ah
57h
is
not
to
to
operation and the system clock from the same oscillator
Configuration bit is not set. Note that the PLL96MHZ
8.5
The 96 MHz PLL block is implemented to generate the
stable 48 MHz clock required for full-speed USB
source. The 96 MHz PLL block is shown in Figure 8-2.
The 96 MHz PLL block requires a 4 MHz input signal; it
uses this to generate a 96 MHz signal from a fixed, 24x
PLL. This is, in turn, divided into two branches. The first
branch generates the USB clock and the second branch
generates the system clock. The 96 MHz PLL block can
be enabled and disabled using the PLL96MHZ Configu-
ration bit (Configuration Word<11>) or through the
PLLEN (CLKDIV<5>) control bit when the PLL96MHZ
Configuration bit and PLLEN register bit are available
only for PIC24F devices with USB.
The 96 MHz PLL prescaler does not automatically
sense the incoming oscillator frequency. The user must
manually configure the PLL divider to generate the
required 4 MHz output, using the PLLDIV<2:0> Config-
uration bits (Configuration Word 2<14:12> in most
devices).
96 MHz PLL Block
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