PIC24FJ256GB206-I/MR Microchip Technology Inc., PIC24FJ256GB206-I/MR Datasheet - Page 95

• Manufacturer Part Number: PIC24FJ256GB206-I/MR
• Description: 16-bit, 256KB Flash, 96K RAM, USB, 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB206-I/MR

• A/d Inputs: 16 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin QFN
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

The CORCON register contains the IPL3 bit, which,
together with IPL<2:0>, indicates the current CPU
priority level. IPL3 is a read-only bit so that trap events
cannot be masked by the user software.
The interrupt controller has the Interrupt Controller Test
register, INTTREG, which displays the status of the
interrupt controller. When an interrupt request occurs,
it’s associated vector number and the new interrupt pri-
ority level are latched into INTTREG. This information
can be used to determine a specific interrupt source if
REGISTER 7-1:
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-9
bit 7-5
Note 1:
R/W-0, HSC
IPL2
U-0
—
2:
3:
(2,3)
See Register 3-1 for the description of the remaining bits (bits 8, 4, 3, 2, 1 and 0) that are not dedicated to
interrupt control functions.
The IPL bits are concatenated with the IPL3 (CORCON<3>) bit to form the CPU interrupt priority level.
The value in parentheses indicates the interrupt priority level if IPL3 = 1.
The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
Unimplemented: Read as ‘0’
IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU interrupt priority level is 7 (15); user interrupts are disabled
110 = CPU interrupt priority level is 6 (14)
101 = CPU interrupt priority level is 5 (13)
100 = CPU interrupt priority level is 4 (12)
011 = CPU interrupt priority level is 3 (11)
010 = CPU interrupt priority level is 2 (10)
001 = CPU interrupt priority level is 1 (9)
000 = CPU interrupt priority level is 0 (8)
R/W-0, HSC R/W-0, HSC
IPL1
U-0
—
SR: ALU STATUS REGISTER (IN CPU)
(2,3)
HSC = Hardware Settable/Clearable bit
W = Writable bit
‘1’ = Bit is set
IPL0
U-0
—
(2,3)
PIC24FJ256GB210 FAMILY
R-0, HSC
RA
U-0
—
(1)
U = Unimplemented bit, read as ‘0’
R/W-0, HSC
‘0’ = Bit is cleared
a generic ISR is used for multiple vectors (such as
when ISR remapping is used in bootloader applica-
tions) or to check if another interrupt is pending while in
an ISR.
All interrupt registers are described in Register 7-1
through Register 7-38 in the succeeding pages.
U-0
N
—
(1)
(2,3)
R/W-0, HSC
OV
U-0
—
(1)
x = Bit is unknown
R/W-0, HSC R/W-0, HSC
U-0
Z
—
(1)
DS39975A-page 95
R-0, HSC
DC
C
(1)
(1)
bit 8
bit 0