PIC24FJ256GB206-I/MR Microchip Technology Inc., PIC24FJ256GB206-I/MR Datasheet - Page 333

• Manufacturer Part Number: PIC24FJ256GB206-I/MR
• Description: 16-bit, 256KB Flash, 96K RAM, USB, 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB206-I/MR

• A/d Inputs: 16 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin QFN
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

26.4.3
The Configuration registers are protected against
inadvertent or unwanted changes or reads in two ways.
The primary protection method is the same as that of
the RP registers – shadow registers contain a compli-
mentary value which is constantly compared with the
actual value.
TABLE 26-2:
26.5
PIC24FJ256GB210 family devices implement a JTAG
interface, which supports boundary scan device
testing.
26.6
PIC24FJ256GB210 family microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock (PGECx)
and data (PGEDx), and three other lines for power
(V
to manufacture boards with unprogrammed devices
and then program the microcontroller just before
shipping the product. This also allows the most recent
firmware or a custom firmware to be programmed.
 2010 Microchip Technology Inc.
DD
WPDIS
Segment Configuration Bits
), ground (V
1
0
0
0
JTAG Interface
In-Circuit Serial Programming™
CONFIGURATION REGISTER
PROTECTION
WPEND
SS
X
1
0
0
CODE SEGMENT PROTECTION CONFIGURATION OPTIONS
) and MCLR. This allows customers
WPCFG
x
x
1
0
No additional protection is enabled; all program memory protection is configured
by GCP and GWRP.
Addresses from the first address of the code page are defined by WPFP<7:0>
through the end of implemented program memory (inclusive), write/erase
protected, including Flash Configuration Words.
Address 000000h through the last address of the code page is defined by
WPFP<7:0> (inclusive), write/erase protected.
Address 000000h through the last address of code page is defined by
WPFP<7:0> (inclusive), write/erase protected and the last page, including Flash
Configuration Words are write/erase protected.
PIC24FJ256GB210 FAMILY
Write/Erase Protection of Code Segment
To safeguard against unpredictable events, Configura-
tion bit changes resulting from individual cell level
disruptions (such as ESD events) will cause a parity
error and trigger a device Reset.
The data for the Configuration registers is derived from
the Flash Configuration Words in program memory.
When the GCP bit is set, the source data for device
configuration is also protected as a consequence. Even
if General Segment protection is not enabled, the
device configuration can be protected by using the
appropriate code segment protection setting.
26.7
When MPLAB
in-circuit debugging functionality is enabled. This func-
tion allows simple debugging functions when used with
MPLAB IDE. Debugging functionality is controlled
through the PGECx (Emulation/Debug Clock) and
PGEDx (Emulation/Debug Data) pins.
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, V
ignated by the ICS Configuration bits. In addition, when
the feature is enabled, some of the resources are not
available for general use. These resources include the
first 80 bytes of data RAM and two I/O pins.
In-Circuit Debugger
DD
, V
®
SS
ICD 3 is selected as a debugger, the
and the PGECx/PGEDx pin pair des-
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