PIC24FJ256GB206-I/MR Microchip Technology Inc., PIC24FJ256GB206-I/MR Datasheet - Page 217

• Manufacturer Part Number: PIC24FJ256GB206-I/MR
• Description: 16-bit, 256KB Flash, 96K RAM, USB, 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB206-I/MR

• A/d Inputs: 16 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin QFN
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

16.0
The Inter-Integrated Circuit™ (I
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be serial EEPROMs, display drivers, A/D
Converters, etc.
The I
• Independent master and slave logic
• 7-bit and 10-bit device addresses
• General call address, as defined in the I
• Clock stretching to provide delays for the
• Both 100 kHz and 400 kHz bus specifications
• Configurable address masking
• Multi-Master modes to prevent loss of messages
• Bus Repeater mode, allowing the acceptance of
• Automatic SCL
A block diagram of the module is shown in Figure 16-1.
 2010 Microchip Technology Inc.
Note:
processor to respond to a slave data request
in arbitration
all messages as a slave regardless of the address
2
C module supports these features:
INTER-INTEGRATED
CIRCUIT™ (I
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
Section 24. “Inter-Integrated Circuit™
(I
this data sheet supersedes the information
in the FRM.
2
C™)” (DS39702). The information in
Family
2
C™)
2
Reference
C™) module is a serial
2
C protocol
Manual”,
PIC24FJ256GB210 FAMILY
16.1
The details of sending a message in Master mode
depends on the communications protocol for the device
being communicated with. Typically, the sequence of
events is as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Wait for and verify an Acknowledge from the
11. Enable master reception to receive serial
12. Generate an ACK or NACK condition at the end
13. Generate a Stop condition on SDAx and SCLx.
Assert a Start condition on SDAx and SCLx.
Send the I
with a write indication.
Wait for and verify an Acknowledge from the
slave.
Send the first data byte (sometimes known as
the command) to the slave.
Wait for and verify an Acknowledge from the
slave.
Send the serial memory address low byte to the
slave.
Repeat steps 4 and 5 until all data bytes are
sent.
Assert a Repeated Start condition on SDAx and
SCLx.
Send the device address byte to the slave with
a read indication.
slave.
memory data.
of a received byte of data.
Communicating as a Master in a
Single Master Environment
2
C device address byte to the slave
DS39975A-page 217