PIC16F72-I/SO Microchip Technology Inc., PIC16F72-I/SO Datasheet - Page 31
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC16F72-I/SO
Manufacturer Part Number
PIC16F72-I/SO
Description
28 PIN, 3.5 KB FLASH, 128 RAM, 22 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F72-ISO.pdf
(136 pages)
Specifications of PIC16F72-I/SO
A/d Inputs
5-Channel, 8-Bit
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Input Output
22
Interface
I2C/SPI
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SOIC
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F72-I/SO
Manufacturer:
MICROCHIP
Quantity:
3 290
Part Number:
PIC16F72-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
5.0
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
Additional information on the Timer0 module is
available in the PICmicro™ Mid-Range MCU Family
Reference Manual (DS33023).
5.1
Timer mode is selected by clearing bit T0CS
(OPTION<5>). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
the TMR0 register is written, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
FIGURE 5-1:
2002 Microchip Technology Inc.
WDT Enable bit
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).
Watchdog
CLKO (= F
Timer
TIMER0 MODULE
Timer0 Operation
RA4/T0CKI
pin
OSC
/4)
T0SE
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
0
1
PSA
M
U
X
0
1
T0CS
M
U
X
0
8-bit Prescaler
8 - to - 1MUX
Time-out
8
M U X
WDT
PRESCALER
1
0
1
PSA
M
U
X
Counter mode is selected by setting bit T0CS
(OPTION<5>). In Counter mode, Timer0 will incre-
ment, either on every rising or falling edge of pin RA4/
T0CKI. The incrementing edge is determined by the
Timer0 Source Edge Select bit T0SE (OPTION<4>).
Clearing bit T0SE selects the rising edge. Restrictions
on the external clock input are discussed in detail in
Section 5.3.
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The pres-
caler is not readable or writable. Section 5.4 details the
operation of the prescaler.
5.2
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
TMR0IF (INTCON<2>). The interrupt can be masked
by clearing bit TMR0IE (INTCON<5>). Bit TMR0IF
must be cleared in software by the Timer0 module
Interrupt Service Routine, before re-enabling this inter-
rupt. The TMR0 interrupt cannot awaken the processor
from SLEEP, since the timer is shut-off during SLEEP.
PSA
PS2:PS0
Timer0 Interrupt
Cycles
SYNC
2
TMR0 reg
Data Bus
PIC16F72
8
Set Flag bit TMR0IF
DS39597B-page 29
on Overflow