PIC16F72-I/SO Microchip Technology Inc., PIC16F72-I/SO Datasheet - Page 39
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PIC16F72-I/SO
Manufacturer Part Number
PIC16F72-I/SO
Description
28 PIN, 3.5 KB FLASH, 128 RAM, 22 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F72-ISO.pdf
(136 pages)
Specifications of PIC16F72-I/SO
A/d Inputs
5-Channel, 8-Bit
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Input Output
22
Interface
I2C/SPI
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SOIC
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F72-I/SO
Manufacturer:
MICROCHIP
Quantity:
3 290
Part Number:
PIC16F72-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
8.0
The CCP (Capture/Compare/PWM) module contains a
16-bit register that can operate as a:
• 16-bit capture register
• 16-bit compare register
• PWM master/slave duty cycle register.
Table 8-1 shows the timer resources of the CCP
Module modes.
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
REGISTER 8-1:
2002 Microchip Technology Inc.
CAPTURE/COMPARE/PWM
(CCP) MODULE
bit 7-6
bit 5-4
bit 3-0
CCPCON1: CAPTURE/COMPARE/PWM CONTROL REGISTER 1 (ADDRESS 17h)
Unimplemented: Read as '0'
CCPxX:CCPxY: PWM Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set,
1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected);
11xx = PWM mode
Legend:
R = Readable bit
- n = Value at POR
bit 7
U-0
—
CCPx pin is unaffected)
CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled)
U-0
—
CCPxX
R/W-0
W = Writable bit
‘1’ = Bit is set
CCPxY
R/W-0
Additional information on the CCP module is available
in the PICmicro™ Mid-Range MCU Reference Manual,
(DS33023).
TABLE 8-1:
CCP Mode
Compare
Capture
CCPxM3
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PWM
R/W-0
CCP MODE - TIMER
RESOURCE
CCPxM2
R/W-0
PIC16F72
Timer Resource
x = Bit is unknown
CCPxM1
R/W-0
DS39597B-page 37
Timer1
Timer1
Timer2
CCPxM0
R/W-0
bit 0