PIC16F72-I/SO Microchip Technology Inc., PIC16F72-I/SO Datasheet - Page 74

• Manufacturer Part Number: PIC16F72-I/SO
• Description: 28 PIN, 3.5 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F72-I/SO

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F72
FIGURE 11-12:
11.15 Program Verification/
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
11.16 ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during program/verify. It is recom-
mended that only the four Least Significant bits of the
ID location are used.
11.17 In-Circuit Serial Programming
PIC16F72 microcontrollers can be serially programmed
while in the end application circuit. This is simply done
with two lines for clock and data and three other lines for
power, ground, and the programming voltage (see
Figure 11-13 for an example). This allows customers to
manufacture boards with unprogrammed devices, and
then program the microcontroller just before shipping
the product. This also allows the most recent firmware
or a custom firmware to be programmed.
For general information of serial programming, please
refer to the In-Circuit Serial Programming™ (ICSP™)
Guide (DS30277). For specific details on programming
commands and operations for the PIC16F72 devices,
please refer to the latest version of the PIC16F72
FLASH Program Memory Programming Specification
(DS39588).
DS39597B-page 72
Note
OSC1
CLKO
INT pin
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
Instruction
Fetched
Instruction
Executed
(4)
1:
2:
3:
4:
Code Protection
PC
XT, HS or LP Oscillator mode assumed.
T
GIE = ‘1' assumed. In this case, after wake-up, the processor jumps to the interrupt routine.
If GIE = ‘0', execution will continue in-line.
CLKO is not available in these Osc modes, but shown here for timing reference.
OST
Inst(PC) = SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Inst(PC - 1)
= 1024 T
PC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
OSC
(drawing not to scale) This delay will not be there for RC Osc mode.
Inst(PC + 1)
SLEEP
PC+1
Processor in
SLEEP
PC+2
T
OST
(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC + 2)
Inst(PC + 1)
FIGURE 11-13:
PC+2
*
External
Connector
Signals
Isolation devices (as required).
Data I/O
CLK
+5V
V
0V
PP
Interrupt Latency
Dummy cycle
(Note 2)
PC + 2
*
To Normal
Connections
To Normal
Connections
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
 2002 Microchip Technology Inc.
Inst(0004h)
Dummy cycle
*
0004h
*
*
V
V
MCLR/V
RB6
RB7
DD
SS
PIC16F72
Inst(0005h)
Inst(0004h)
0005h
V
PP
DD