PIC16F72-I/SO Microchip Technology Inc., PIC16F72-I/SO Datasheet - Page 72
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PIC16F72-I/SO
Manufacturer Part Number
PIC16F72-I/SO
Description
28 PIN, 3.5 KB FLASH, 128 RAM, 22 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F72-ISO.pdf
(136 pages)
Specifications of PIC16F72-I/SO
A/d Inputs
5-Channel, 8-Bit
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Input Output
22
Interface
I2C/SPI
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SOIC
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F72-I/SO
Manufacturer:
MICROCHIP
Quantity:
3 290
Part Number:
PIC16F72-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC16F72
11.13 Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip RC
oscillator that does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKI pin. That means that the WDT
will run, even if the clock on the OSC1/CLKI and OSC2/
CLKO pins of the device has been stopped, for
example, by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watchdog
Timer Wake-up). The TO bit in the STATUS register will
be cleared upon a Watchdog Timer time-out.
The WDT can be permanently disabled by clearing
configuration bit WDTEN (see Section 11.1).
FIGURE 11-11:
TABLE 11-7:
DS39597B-page 70
2007h
81h,181h
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 11-1 for operation of these bits.
Address
Note: PSA and PS2:PS0 are bits in the OPTION register.
Config. bits
OPTION
Name
SUMMARY OF WATCHDOG TIMER REGISTERS
WDT Timer
Enable Bit
WATCHDOG TIMER BLOCK DIAGRAM
WDT
From TMR0 Clock Source
(Figure 5-1)
RBPU
Bit 7
(1)
BOREN
INTEDG
Bit 6
0
1
PSA
(1)
M
U
X
T0CS
Bit 5
—
T0SE
0
Bit 4
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION register.
CP
Time-out
8 - to - 1 MUX
MUX
Note 1: The CLRWDT and SLEEP instructions
WDT
Postscaler
PWRTEN
2: When a CLRWDT instruction is executed
1
8
Bit 3
PSA
clear the WDT and the postscaler, if
assigned to the WDT, and prevent it from
timing out and generating a device
RESET condition.
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but
the prescaler assignment is not changed.
(1)
PSA
To TMR0 (Figure 5-1)
WDTEN
Bit 2
PS2
2002 Microchip Technology Inc.
PS2:PS0
FOSC1
Bit 1
PS1
FOSC0
Bit 0
PS0