PIC16F72-I/SO Microchip Technology Inc., PIC16F72-I/SO Datasheet - Page 75

• Manufacturer Part Number: PIC16F72-I/SO
• Description: 28 PIN, 3.5 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F72-I/SO

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

12.0
Each PIC16F72 instruction is a 14-bit word divided into
an OPCODE that specifies the instruction type and one
or more operands that further specify the operation of
the instruction. The PIC16F72 instruction set summary
in Table 12-2 lists byte-oriented, bit-oriented, and lit-
eral and control operations. Table 12-1 shows the
opcode field descriptions.
For byte-oriented instructions, ‘f’ represents a file reg-
ister designator and ‘d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ‘f’ represents the number of the
file in which the bit is located.
For literal and control operations, ‘k’ represents an
eight or eleven-bit constant or literal value.
TABLE 12-1:
The instruction set is highly orthogonal and is grouped
into three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles,
with the second cycle executed as a
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 µs. If a conditional test is true, or the
program counter is changed as a result of an
instruction, the instruction execution time is 2 µs.
 2002 Microchip Technology Inc.
Field
PC
TO
PD
f
W
b
k
x
d
Register file address (0x00 to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
Don’t care location (= 0 or 1).
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
Program Counter
Time-out bit
Power-down bit
INSTRUCTION SET SUMMARY
OPCODE FIELD
DESCRIPTIONS
Description
NOP
. One instruc-
Table 12-2 lists the instructions recognized by the
MPASM
Figure 12-1 shows the general formats that the
instructions can have.
All examples use the following format to represent a
hexadecimal number:
where h signifies a hexadecimal digit.
FIGURE 12-1:
A description of each instruction is available in the
PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
Byte-oriented file register operations
Bit-oriented file register operations
Literal and control operations
General
CALL and GOTO instructions only
0xhh
13
13
13
13
TM
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
b = 3-bit bit address
f = 7-bit file register address
k = 8-bit immediate value
k = 11-bit immediate value
OPCODE
assembler.
OPCODE
OPCODE
OPCODE
11
10
10 9
GENERAL FORMAT FOR
INSTRUCTIONS
8
b (BIT #)
d
7
8
PIC16F72
6
7
7 6
k (literal)
f (FILE #)
DS39597B-page 73
k (literal)
f (FILE #)
0
0
0
0